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raw | patch | inline | side by side (parent: 5db5aaa)
bigint shuffle
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 22 Oct 2022 16:15:17 +0000 (17:15 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 2 Jun 2023 18:51:15 +0000 (19:51 +0100)
* divmod2du moves to XO=58 (from XO=52)
* dsld/dsrd become Rc=1 and move to XO=52-55 in VA2-Form
* dsld/dsrd pseudocode no longer is overwrite with "sm" mode
* Z23 "sm" removed from fields.txt

openpower/isa/svfixedarith.mdwn patch | blob | history
openpower/isatables/RM-1P-2S1D.csv patch | blob | history
openpower/isatables/RM-1P-3S1D.csv patch | blob | history
openpower/isatables/fields.text patch | blob | history
openpower/isatables/minor_31.csv patch | blob | history
openpower/isatables/minor_4.csv patch | blob | history
src/openpower/decoder/power_decoder2.py patch | blob | history
src/openpower/sv/trans/svp64.py patch | blob | history
src/openpower/sv/trans/test_pysvp64dis.py patch | blob | history
src/openpower/test/bigint/bigint_cases.py patch | blob | history

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index bb9ffc6e35e9bace3721521ff23a93ded18b49ce..b3728bf554828177bf46ec59f732c19b91c368ee 100644 (file)
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -48,30 +48,16 @@ Special Registers Altered:
 
 # [DRAFT] Double-width Shift Left Doubleword
 
-Z23-Form
+VA2-Form
 
-* dsld    RT,RA,RB,sm  (Rc=0)
-* dsld.   RT,RA,RB,sm  (Rc=1)
+* dsld    RT,RA,RB,RC  (Rc=0)
+* dsld.   RT,RA,RB,RC  (Rc=1)
 
 Pseudo-code:
 
-    switch(sm)
-        case(0):
-            hi <- (RT)
-            lo <- (RA)
-            sh <- (RB)
-        case(1):
-            hi <- (RA)
-            lo <- (RT)
-            sh <- (RB)
-        case(2):
-            hi <- (RA)
-            lo <- (RB)
-            sh <- (RT)
-        default:
-            hi <- [0] * 64
-            lo <- (RA)
-            sh <- (RB)
+    hi <- (RC)
+    lo <- (RA)
+    sh <- (RB)
     n <- sh[58:63]
     mask[0:63] <- MASK(n, 63)
     v[0:63] <- (hi & mask) | (lo & ¬mask)
@@ -83,30 +69,16 @@ Special Registers Altered:
 
 # [DRAFT] Double-width Shift Right Doubleword
 
-Z23-Form
+VA2-Form
 
-* dsrd    RT,RA,RB,sm  (Rc=0)
-* dsrd.   RT,RA,RB,sm  (Rc=1)
+* dsrd    RT,RA,RB,RC  (Rc=0)
+* dsrd.   RT,RA,RB,RC  (Rc=1)
 
 Pseudo-code:
 
-    switch(sm)
-        case(0):
-            hi <- (RT)
-            lo <- (RA)
-            sh <- (RB)
-        case(1):
-            hi <- (RA)
-            lo <- (RT)
-            sh <- (RB)
-        case(2):
-            hi <- (RA)
-            lo <- (RB)
-            sh <- (RT)
-        default:
-            hi <- (RA)
-            lo <- [0] * 64
-            sh <- (RB)
+    hi <- (RC)
+    lo <- (RA)
+    sh <- (RB)
     n <- sh[58:63]
     mask[0:63] <- MASK(0, 63 - n)
     v[0:63] <- (hi & ¬mask) | (lo & mask)
diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv
index 2e8a32c934f70ecf3cbdb6292951920035183ef0..5c0c41c31e29715e823af22d7505d157116a402c 100644 (file)
--- a/openpower/isatables/RM-1P-2S1D.csv
+++ b/openpower/isatables/RM-1P-2S1D.csv
@@ -43,7 +43,6 @@ slw,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
 sld,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
 and,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
 subf,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-dsld,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 andc,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
 mulhd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 addg6s,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
@@ -51,19 +50,16 @@ mulhw,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 nor,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
 subfe,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 adde,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-dsrd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 mulld,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 mullw,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 add,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 eqv,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
-dsld,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 xor,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
 divdeu,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 divweu,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 orc,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
 divde,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 divwe,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-dsrd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 or,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
 divdu,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 divwu,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
@@ -77,23 +73,19 @@ mulhwu,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 srw,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
 srd,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
 subfo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-dsld,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 mulhd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 mulhw,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 subfeo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 addeo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-dsrd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 mulldo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 mullwo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 addo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 sraw,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
 srad,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
-dsld,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 divdeuo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 divweuo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 divdeo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 divweo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-dsrd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 divduo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 divwuo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
 divdo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
diff --git a/openpower/isatables/RM-1P-3S1D.csv b/openpower/isatables/RM-1P-3S1D.csv
index 31105cf77abd86e7efbbd7e2c9ffd130a2e4f32a..09eebc6a12b335beb1e91b50e159520e84135ab0 100644 (file)
--- a/openpower/isatables/RM-1P-3S1D.csv
+++ b/openpower/isatables/RM-1P-3S1D.csv
@@ -38,6 +38,10 @@ maddld,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
 divmod2du,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
 absdacs,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0
 absdacu,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0
+dsld,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0
+dsld,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0
+dsrd,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0
+dsrd,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0
 pcdec,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0
 ternlogi,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0
 ffmsubs,NORMAL,,1P,EXTRA2,NO,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text
index f035b438baa8df9933f44cfcdbaf8fe93eab355d..22c11cd2843a11696de8279ab1665790783e5142 100644 (file)
--- a/openpower/isatables/fields.text
+++ b/openpower/isatables/fields.text
@@ -271,7 +271,6 @@
     | PO   |  FRT |    TE    |   FRB |RMC|   XO |Rc |
     | PO   |  FRTp|    TE    |  FRBp |RMC|   XO |Rc |
     | PO   |  FRT |   FRA    |   FRB |RMC|   XO |Rc |
-    | PO   |  RT  |   RA     |   RB  |sm |   XO |Rc |
     | PO   |  RT  |   RA     |   RB  |CY |   XO |Rc |
     | PO   |  FRTp|   FRA    |  FRBp |RMC|   XO |Rc |
     | PO   |  FRTp|  FRAp    |  FRBp |RMC|   XO |Rc |
@@ -788,9 +787,6 @@
     SCi (11:31)
         SV Context Propagation immediate bitfield
         Formats: SVC
-    sm (21:22)
-        Immediate field used for selecting operands (shift mode)
-        Formats: Z23
     SRb (11:14)
         SV REMAP byte-reversal field.
         Formats: SVC
diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv
index 1c67cbe7a585b00b1dbcb4fdb8ee632ec7c34a48..e4dd1ce47c1142f76e5531ef30bc572e918f8b79 100644 (file)
--- a/openpower/isatables/minor_31.csv
+++ b/openpower/isatables/minor_31.csv
@@ -208,11 +208,3 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b1000110110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,tlbsync,X,,,
 0b0000011110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,wait,X,,,
 0b0100111100,LOGICAL,OP_XOR,RS,RB,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,xor,X,,,
-0b0000111001,SHIFT_ROT,OP_DSHL,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0b0100111001,SHIFT_ROT,OP_DSHL,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0b1000111001,SHIFT_ROT,OP_DSHL,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0b1100111001,SHIFT_ROT,OP_DSHL,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0b0010111001,SHIFT_ROT,OP_DSHR,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0b0110111001,SHIFT_ROT,OP_DSHR,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0b1010111001,SHIFT_ROT,OP_DSHR,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0b1110111001,SHIFT_ROT,OP_DSHR,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg
diff --git a/openpower/isatables/minor_4.csv b/openpower/isatables/minor_4.csv
index f4bfc6c77471e0e5ca6649406508a8a9cb79a5fa..b2426340b1da02f05248bedcce75ee4eb7ed6db7 100644 (file)
--- a/openpower/isatables/minor_4.csv
+++ b/openpower/isatables/minor_4.csv
@@ -5,5 +5,9 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 49,ALU,OP_MADDHDU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddhdu,VA,,,
 50,ALU,OP_MADDEDU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddedu,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 51,ALU,OP_MADDLD,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddld,VA,,,
-52,ALU,OP_DIVMOD2DU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,divmod2du,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+58,ALU,OP_DIVMOD2DU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,divmod2du,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 56,ALU,OP_PCDEC,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,ONE,0,0,pcdec,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+52,SHIFT_ROT,OP_DSHL,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+53,SHIFT_ROT,OP_DSHL,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+54,SHIFT_ROT,OP_DSHR,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+55,SHIFT_ROT,OP_DSHR,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 5e7b03706bcaf3396e54ed78fcca641ab159853d..ca2247c187f1e86a684643445af2671911ad2508 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -1057,7 +1057,7 @@ class PowerDecodeSubset(Elaboratable):
             with m.If((major == 4) & xo6.matches(
                     '111000',  # pcdec
                     '110010',  # maddedu
-                    '110100',  # divmod2du
+                    '111010',  # divmod2du
                 )):
                 comb += self.implicit_rs.eq(1)
                 comb += self.extend_rc_maxvl.eq(1) # RS=RT+MAXVL or RS=RC
diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index a798085e57b7c2913e819560213c49c34a1493b9..f37d5a6b4c15c9683ffcafa93cc9c4cce72a9246 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -566,7 +566,7 @@ def fishmv(fields):
 
 @_custom_insns(
     _insn("maddedu", XO=50),
-    _insn("divmod2du", XO=52),
+    _insn("divmod2du", XO=58),
     _insn("pcdec.", XO=56),
 )
 def va_form(fields, XO):
@@ -587,25 +587,25 @@ def va_form(fields, XO):
 
 
 @_custom_insns(
-    _insn("dsld",  XO=0b00111001, Rc=0),
-    _insn("dsld.", XO=0b00111001, Rc=1),
-    _insn("dsrd",  XO=0b10111001, Rc=0),
-    _insn("dsrd.", XO=0b10111001, Rc=1),
+    _insn("dsld",  XO=26, Rc=0), # minor_4=52 (26<<1 | Rc=0)
+    _insn("dsld.", XO=26, Rc=1), # minor_4=53 (26<<1 | Rc=1)
+    _insn("dsrd",  XO=27, Rc=0), # minor_4=54 (27<<1 | Rc=0)
+    _insn("dsrd.", XO=27, Rc=1), # minor_4=55 (27<<1 | Rc=1)
 )
 def dsld_dsrd(fields, XO, Rc):
     # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
-    # 1.6.27 Z23-FORM
-    #   |0     |6     |11    |15 |16     |21 |23    |31 |
-    #   | PO   |  RT  |   RA     |   RB  |sm |   XO |Rc |
-    PO = 31
-    (RT, RA, RB, sm) = fields
+    # 1.6.21.1 VA2-FORM
+    #    |0   |6   |11   |16   |21  |26  |31|
+    #    | PO | RT |  RA |  RB | RC | XO |Rc|
+    PO = 4
+    (RT, RA, RB, RC) = fields
     return instruction(
         (PO, 0, 5),
         (RT, 6, 10),
         (RA, 11, 15),
         (RB, 16, 20),
-        (sm, 21, 22),
-        (XO, 23, 30),
+        (RC, 21, 25),
+        (XO, 26, 30),
         (Rc, 31, 31),
     )
 
@@ -1754,7 +1754,9 @@ if __name__ == '__main__':
         'pcdec. 0,0,0,0',
     ]
     lst = [
-        "sv.cmp/ff=gt *0,*1,*2,0",
+        #"sv.cmp/ff=gt *0,*1,*2,0",
+        "dsld 5,4,5,3",
+
     ]
     isa = SVP64Asm(lst, macros=macros)
     log("list:\n", "\n\t".join(list(isa)))
diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 3ffcbc8eb4ffe0ea42ecebc916742f57cf69dc0d..662871b2c06f832c2b0dc499a00d540c16c37683 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -397,6 +397,25 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
+    def test_29_dsld_dsrd(self):
+        expected = [
+                    "dsld 5,4,5,3",
+                    "dsrd 5,4,5,3",
+                    "dsld. 5,4,5,3",
+                    "dsrd. 5,4,5,3",
+                    "sv.dsld *6,4,5,3",
+                    "sv.dsrd *6,4,5,3",
+                    "sv.dsld. *6,4,5,3",
+                    "sv.dsrd. *6,4,5,3",
+                        ]
+        self._do_tst(expected)
+
+    def test_30_divmod2du(self):
+        expected = [
+                    "divmod2du 5,4,5,3",
+                        ]
+        self._do_tst(expected)
+
 
 if __name__ == "__main__":
     unittest.main()
diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py
index b6d86322d0d05b93eb23b5f26307b6aff22939a0..f066e40d68b365e51053bf711ad705a4a91af03f 100644 (file)
--- a/src/openpower/test/bigint/bigint_cases.py
+++ b/src/openpower/test/bigint/bigint_cases.py
@@ -34,7 +34,7 @@ class BigIntCases(TestAccumulatorBase):
     # FIXME: test more divmod2du special cases
 
     def case_dsld0(self):
-        prog = Program(list(SVP64Asm(["dsld 3,4,5,0"])), False)
+        prog = Program(list(SVP64Asm(["dsld 3,4,5,3"])), False)
         for sh in _SHIFT_TEST_RANGE:
             with self.subTest(sh=sh):
                 gprs = [0] * 32
@@ -48,7 +48,7 @@ class BigIntCases(TestAccumulatorBase):
                 self.add_case(prog, gprs, expected=e)
 
     def case_dsld1(self):
-        prog = Program(list(SVP64Asm(["dsld 3,4,5,1"])), False)
+        prog = Program(list(SVP64Asm(["dsld 3,3,5,4"])), False)
         for sh in _SHIFT_TEST_RANGE:
             with self.subTest(sh=sh):
                 gprs = [0] * 32
@@ -62,7 +62,7 @@ class BigIntCases(TestAccumulatorBase):
                 self.add_case(prog, gprs, expected=e)
 
     def case_dsld2(self):
-        prog = Program(list(SVP64Asm(["dsld 3,4,5,2"])), False)
+        prog = Program(list(SVP64Asm(["dsld 3,5,3,4"])), False)
         for sh in _SHIFT_TEST_RANGE:
             with self.subTest(sh=sh):
                 gprs = [0] * 32
@@ -75,22 +75,8 @@ class BigIntCases(TestAccumulatorBase):
                 e.intregs[3] = (v >> 64) % 2 ** 64
                 self.add_case(prog, gprs, expected=e)
 
-    def case_dsld3(self):
-        prog = Program(list(SVP64Asm(["dsld 3,4,5,3"])), False)
-        for sh in _SHIFT_TEST_RANGE:
-            with self.subTest(sh=sh):
-                gprs = [0] * 32
-                gprs[3] = 0x123456789ABCDEF
-                gprs[4] = 0xFEDCBA9876543210
-                gprs[5] = sh % 2 ** 64
-                e = ExpectedState(pc=4, int_regs=gprs)
-                v = gprs[4]
-                v <<= sh % 64
-                e.intregs[3] = (v >> 64) % 2 ** 64
-                self.add_case(prog, gprs, expected=e)
-
     def case_dsrd0(self):
-        prog = Program(list(SVP64Asm(["dsrd 3,4,5,0"])), False)
+        prog = Program(list(SVP64Asm(["dsrd 3,4,5,3"])), False)
         for sh in _SHIFT_TEST_RANGE:
             with self.subTest(sh=sh):
                 gprs = [0] * 32
@@ -104,7 +90,7 @@ class BigIntCases(TestAccumulatorBase):
                 self.add_case(prog, gprs, expected=e)
 
     def case_dsrd1(self):
-        prog = Program(list(SVP64Asm(["dsrd 3,4,5,1"])), False)
+        prog = Program(list(SVP64Asm(["dsrd 3,3,5,4"])), False)
         for sh in _SHIFT_TEST_RANGE:
             with self.subTest(sh=sh):
                 gprs = [0] * 32
@@ -118,7 +104,7 @@ class BigIntCases(TestAccumulatorBase):
                 self.add_case(prog, gprs, expected=e)
 
     def case_dsrd2(self):
-        prog = Program(list(SVP64Asm(["dsrd 3,4,5,2"])), False)
+        prog = Program(list(SVP64Asm(["dsrd 3,5,3,4"])), False)
         for sh in _SHIFT_TEST_RANGE:
             with self.subTest(sh=sh):
                 gprs = [0] * 32