/* Default to no tiling */
region->tiling = I915_TILING_NONE;
- region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
_DBG("%s <-- %p\n", __FUNCTION__, region);
return region;
region = intel_region_alloc_internal(intel, cpp, width, height,
pitch, buffer);
-
- if (tiling != I915_TILING_NONE) {
- assert(((pitch * cpp) & 127) == 0);
- drm_intel_bo_set_tiling(buffer, &tiling, pitch * cpp);
- drm_intel_bo_get_tiling(buffer, ®ion->tiling, ®ion->bit_6_swizzle);
- }
+ region->tiling = tiling;
return region;
}
struct intel_region *region, *dummy;
dri_bo *buffer;
int ret;
+ uint32_t bit_6_swizzle;
region = _mesa_HashLookup(intel->intelScreen->named_regions, handle);
if (region != NULL) {
return region;
ret = dri_bo_get_tiling(region->buffer, ®ion->tiling,
- ®ion->bit_6_swizzle);
+ &bit_6_swizzle);
if (ret != 0) {
fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n",
handle, name, strerror(-ret));
GLuint draw_x, draw_y; /**< Offset of drawing within the region */
uint32_t tiling; /**< Which tiling mode the region is in */
- uint32_t bit_6_swizzle; /**< GEM flag for address swizzling requirement */
struct intel_buffer_object *pbo; /* zero-copy uploads */
uint32_t name; /**< Global name for the bo */