revamp hwacha tests

diff --git a/env/pt/pcr.h b/env/pt/pcr.h
deleted file mode 100644 (file)
index 72043b7..0000000
--- a/env/pt/pcr.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef _RISCV_PCR_H
-#define _RISCV_PCR_H
-
-#define SR_ET    0x00000001
-#define SR_EF    0x00000002
-#define SR_EV    0x00000004
-#define SR_EC    0x00000008
-#define SR_PS    0x00000010
-#define SR_S     0x00000020
-#define SR_U64   0x00000040
-#define SR_S64   0x00000080
-#define SR_VM    0x00000100
-#define SR_IM    0x00FF0000
-#define SR_ZERO  ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_U64|SR_S64|SR_VM|SR_IM)
-#define SR_IM_SHIFT 16
-
-#define PCR_SR       0
-#define PCR_EPC      1
-#define PCR_BADVADDR 2
-#define PCR_EVEC     3
-#define PCR_COUNT    4
-#define PCR_COMPARE  5
-#define PCR_CAUSE    6
-#define PCR_PTBR     7
-#define PCR_SEND_IPI 8
-#define PCR_CLR_IPI  9
-#define PCR_COREID   10
-#define PCR_IMPL     11
-#define PCR_K0       12
-#define PCR_K1       13
-#define PCR_VECBANK  18
-#define PCR_VECCFG   19
-#define PCR_RESET    29
-#define PCR_TOHOST   30
-#define PCR_FROMHOST 31
-
-#define IMPL_ISASIM 1
-#define IMPL_ROCKET 2
-
-#define IRQ_IPI   5
-#define IRQ_TIMER 7
-
-#define CAUSE_MISALIGNED_FETCH 0
-#define CAUSE_FAULT_FETCH 1
-#define CAUSE_ILLEGAL_INSTRUCTION 2
-#define CAUSE_PRIVILEGED_INSTRUCTION 3
-#define CAUSE_FP_DISABLED 4
-#define CAUSE_SYSCALL 6
-#define CAUSE_BREAKPOINT 7
-#define CAUSE_MISALIGNED_LOAD 8
-#define CAUSE_MISALIGNED_STORE 9
-#define CAUSE_FAULT_LOAD 10
-#define CAUSE_FAULT_STORE 11
-#define CAUSE_VECTOR_DISABLED 12
-#define CAUSE_VECTOR_BANK 13
-
-#define CAUSE_VECTOR_MISALIGNED_FETCH 24
-#define CAUSE_VECTOR_FAULT_FETCH 25
-#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26
-#define CAUSE_VECTOR_ILLEGAL_COMMAND 27
-#define CAUSE_VECTOR_MISALIGNED_LOAD 28
-#define CAUSE_VECTOR_MISALIGNED_STORE 29
-#define CAUSE_VECTOR_FAULT_LOAD 30
-#define CAUSE_VECTOR_FAULT_STORE 31
-
-#ifdef __riscv
-
-#define ASM_CR(r)   _ASM_CR(r)
-#define _ASM_CR(r)  cr##r
-
-#ifndef __ASSEMBLER__
-
-#define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \
-          asm volatile ("mtpcr %0,%1,cr%2" : "=r"(__tmp2) : "r"(__tmp),"i"(reg)); \
-          __tmp2; })
-
-#define mfpcr(reg) ({ long __tmp; \
-          asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \
-          __tmp; })
-
-#define setpcr(reg,val) ({ long __tmp; \
-          asm volatile ("setpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
-          __tmp; })
-
-#define clearpcr(reg,val) ({ long __tmp; \
-          asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
-          __tmp; })
-
-#endif
-
-#endif
-
-#endif

diff --git a/env/pt/riscv_test.h b/env/pt/riscv_test.h
index 822dcfaebb876281e98e9d616f5ada2206500428..e56267f598c650c985bb9158c05d06aaac8feda7 100644 (file)
--- a/env/pt/riscv_test.h
+++ b/env/pt/riscv_test.h
@@ -81,21 +81,20 @@ evac:                              \
 //-----------------------------------------------------------------------
 
 #define ENABLE_TIMER_INTERRUPT \
-        mtpcr x0,ASM_CR(PCR_CLR_IPI);\
-        mfpcr a0,ASM_CR(PCR_SR);     \
-        li a1, SR_ET|SR_IM;          \
-        or a0,a0,a1;                 \
-        mtpcr a0,ASM_CR(PCR_SR);     \
+        mtpcr x0,clear_ipi;          \
+        mfpcr a0,status;             \
+        li a1,SR_IM;                 \
+        mtpcr a0,status;             \
         la a0,_handler;              \
-        mtpcr a0,ASM_CR(PCR_EVEC);   \
-        mtpcr x0,ASM_CR(PCR_COUNT);  \
+        mtpcr a0,evec;               \
+        mtpcr x0,count;              \
         addi a0,x0,60;               \
-        mtpcr a0,ASM_CR(PCR_COMPARE);\
+        mtpcr a0,compare;            \
 
 #define XCPT_HANDLER \
 _handler: \
-        mtpcr a0,ASM_CR(PCR_K0);     \
-        mtpcr a1,ASM_CR(PCR_K1);     \
+        mtpcr a0,sup0;               \
+        mtpcr a1,sup1;               \
         la a0,regspill;              \
         sd a2,0(a0);                 \
         sd a3,8(a0);                 \
@@ -103,19 +102,12 @@ _handler: \
         sd a5,24(a0);                \
         sd s0,32(a0);                \
         sd s1,40(a0);                \
-        mfpcr s1,ASM_CR(PCR_VECBANK);\
-        mfpcr s0,ASM_CR(PCR_VECCFG); \
+        vgetcfg s0;                  \
+        vgetvl s1;                   \
         la a0,evac;                  \
         vxcptevac a0;                \
-        mtpcr s1,ASM_CR(PCR_VECBANK);\
-        srli a1,s0,12;               \
-        andi a1,a1,0x3f;             \
-        srli a2,s0,18;               \
-        andi a2,a2,0x3f;             \
-        vvcfg a1,a2;                 \
-        li a2,0xfff;                 \
-        and a1,s0,a2;                \
-        vsetvl a1,a1;                \
+        vsetcfg s0;                  \
+        vsetvl s1,s1;                \
         vxcpthold;                   \
         li a5,0;                     \
 _handler_loop: \
@@ -167,11 +159,11 @@ _done_skip: \
         ld a5,24(a0);                \
         ld s0,32(a0);                \
         ld s1,40(a0);                \
-        mfpcr a0,ASM_CR(PCR_COUNT);  \
+        mfpcr a0,count;              \
         addi a0,a0,60;               \
-        mtpcr a0,ASM_CR(PCR_COMPARE);\
-        mfpcr a0,ASM_CR(PCR_K0);     \
-        mfpcr a1,ASM_CR(PCR_K1);     \
+        mtpcr a0,compare;            \
+        mfpcr a0,sup0;               \
+        mfpcr a1,sup1;               \
         eret;                        \
 
 #endif

diff --git a/isa/Makefile b/isa/Makefile
index 553e692e6c90028c66212d1ada33aa6de14c9a70..f165c38339abcc8a37b362b43e17b59f8ca1b368 100644 (file)
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -6,9 +6,9 @@ isa_src_dir := .
 
 include $(isa_src_dir)/rv64ui/Makefrag
 include $(isa_src_dir)/rv64uf/Makefrag
-#include $(isa_src_dir)/rv64uv/Makefrag
+include $(isa_src_dir)/rv64uv/Makefrag
 include $(isa_src_dir)/rv64si/Makefrag
-#include $(isa_src_dir)/rv64sv/Makefrag
+include $(isa_src_dir)/rv64sv/Makefrag
 include $(isa_src_dir)/rv32ui/Makefrag
 
 default: all
@@ -54,17 +54,17 @@ $$($(1)_v_tests): $(1)-v-%: $(1)/%.S
        $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -std=gnu99 -O2 -I$(isa_src_dir)/../env/v -I$(isa_src_dir)/macros/scalar -T$(isa_src_dir)/../env/v/link.ld $(isa_src_dir)/../env/v/entry.S $(isa_src_dir)/../env/v/vm.c $$< -lc -o $$@
 tests += $$($(1)_v_tests)
 
-#$$($(1)_p_vec_tests): $(1)-p-vec-%: $(1)/%.S
-#      $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(isa_src_dir)/../env/p -I$(isa_src_dir)/macros/vector -T$(isa_src_dir)/../env/p/link.ld $$< -o $$@
-#tests += $$($(1)_p_vec_tests)
-#
-#$$($(1)_pt_vec_tests): $(1)-pt-vec-%: $(1)/%.S
-#      $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(isa_src_dir)/../env/pt -I$(isa_src_dir)/macros/vector -T$(isa_src_dir)/../env/pt/link.ld $$< -o $$@
-#tests += $$($(1)_pt_vec_tests)
-#
-#$$($(1)_v_vec_tests): $(1)-v-vec-%: $(1)/%.S
-#      $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -std=gnu99 -O2 -I$(isa_src_dir)/../env/v -I$(isa_src_dir)/macros/vector -T$(isa_src_dir)/../env/v/link.ld $(isa_src_dir)/../env/v/entry.S $(isa_src_dir)/../env/v/vm.c $$< -lc -o $$@
-#tests += $$($(1)_v_vec_tests)
+$$($(1)_p_vec_tests): $(1)-p-vec-%: $(1)/%.S
+       $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(isa_src_dir)/../env/p -I$(isa_src_dir)/macros/vector -T$(isa_src_dir)/../env/p/link.ld $$< -o $$@
+tests += $$($(1)_p_vec_tests)
+
+$$($(1)_pt_vec_tests): $(1)-pt-vec-%: $(1)/%.S
+       $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(isa_src_dir)/../env/pt -I$(isa_src_dir)/macros/vector -T$(isa_src_dir)/../env/pt/link.ld $$< -o $$@
+tests += $$($(1)_pt_vec_tests)
+
+$$($(1)_v_vec_tests): $(1)-v-vec-%: $(1)/%.S
+       $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -std=gnu99 -O2 -I$(isa_src_dir)/../env/v -I$(isa_src_dir)/macros/vector -T$(isa_src_dir)/../env/v/link.ld $(isa_src_dir)/../env/v/entry.S $(isa_src_dir)/../env/v/vm.c $$< -lc -o $$@
+tests += $$($(1)_v_vec_tests)
 
 endef
 
@@ -75,8 +75,8 @@ $(eval $(call compile_template,rv64uv))
 $(eval $(call compile_template,rv64si))
 $(eval $(call compile_template,rv64sv))
 
-tests_dump = $(addsuffix .dump, $(spike_tests))
-tests_hex = $(addsuffix .hex, $(spike_tests))
+tests_dump = $(addsuffix .dump, $(tests))
+tests_hex = $(addsuffix .hex, $(tests))
 tests_out = $(addsuffix .out, $(spike_tests))
 
 run: $(tests_out)

diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h
index 6ce6abc43a6b2e6886d57b4d221afa9e804972bd..7da0b59accd66a42fa4048bc4dc4afb8d6500aee 100644 (file)
--- a/isa/macros/scalar/test_macros.h
+++ b/isa/macros/scalar/test_macros.h
@@ -96,30 +96,26 @@ pass_ ## testnum: \
 # Tests for vector config instructions
 #-----------------------------------------------------------------------
 
-#define TEST_VVCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \
+#define TEST_VSETCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \
     TEST_CASE_JUMP( testnum, x1, result, \
-      li x2, bank; \
-      mtpcr x2, cr18; \
+      li x1, (bank << 12); \
+      vsetcfg x1,nxpr,nfpr; \
       li x1, vl; \
-      vvcfgivl x1,x1,nxpr,nfpr; \
+      vsetvl x1,x1; \
     )
 
 #define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \
     TEST_CASE_JUMP( testnum, x1, result, \
-      li x2, bank; \
-      mtpcr x2, cr18; \
-      li x1, nxpr; \
-      li x2, nfpr; \
-      vvcfg x1,x2; \
+      li x1, (bank << 12) | (nfpr << 6) | nxpr; \
+      vsetcfg x1; \
       li x1, vl; \
       vsetvl x1,x1; \
     )
 
 #define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \
     TEST_CASE_JUMP( testnum, x1, result, \
-      li x2, bank; \
-      mtpcr x2, cr18; \
-      vvcfgivl x0,x0,nxpr,nfpr; \
+      li x1, (bank << 12); \
+      vsetcfg x1,nxpr,nfpr; \
       li x1, vl; \
       vsetvl x1, x1; \
     )
@@ -567,15 +563,11 @@ test_ ## testnum: \
 #-----------------------------------------------------------------------
 
 #define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
-  mfpcr a0,cr0; \
-  li a1,1; \
-  slli a3,a1,8; \
-  or a0,a0,a1; \
-  mtpcr a0,cr0; \
   la a0, handler ## testnum; \
-  mtpcr a0, cr3; \
+  mtpcr a0, evec; \
+  vsetcfg nxreg, nfreg; \
   li a0, 4; \
-  vvcfgivl a0, a0, nxreg, nfreg; \
+  vsetvl a0, a0; \
   la a0, src1; \
   la a1, src2; \
   vld vx2, a0; \
@@ -584,7 +576,7 @@ test_ ## testnum: \
   vf %lo(vtcode1 ## testnum)(a0); \
   la a3, dest; \
   vsd vx2, a3; \
-  fence.v.l; \
+  fence; \
 vtcode1 ## testnum: \
   add x2, x2, x3; \
 illegal ## testnum: \
@@ -602,8 +594,9 @@ handler ## testnum: \
   mfpcr a0,cr2; \
   la a1,illegal ## testnum; \
   bne a0,a1,fail; \
+  vsetcfg 32,0; \
   li a0,4; \
-  vvcfgivl a0,a0,32,0; \
+  vsetvl a0,a0; \
   la a0,src1; \
   la a1,src2; \
   vld vx2,a0; \
@@ -612,7 +605,7 @@ handler ## testnum: \
   vf %lo(vtcode2 ## testnum)(a0); \
   la a3,dest; \
   vsd vx2,a3; \
-  fence.v.l; \
+  fence; \
   ld a1,0(a3); \
   li a2,5; \
   li x28,2; \
@@ -628,15 +621,11 @@ handler ## testnum: \
   bne a1,a2,fail; \
 
 #define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, aux) \
-  mfpcr a0,cr0; \
-  li a1,1; \
-  slli a2,a1,8; \
-  or a0,a0,a1; \
-  mtpcr a0,cr0; \
   la a0, handler ## testnum; \
-  mtpcr a0, cr3; \
+  mtpcr a0, evec; \
+  vsetcfg nxreg, nfreg; \
   li a0, 4; \
-  vvcfgivl a0, a0, nxreg, nfreg; \
+  vsetvl a0, a0; \
   la a0, src1; \
   la a1, src2; \
   vld vx2, a0; \
@@ -648,7 +637,7 @@ illegal ## testnum: \
   inst reg1, reg2; \
   la a3, dest; \
   vsd vx2, a3; \
-  fence.v.l; \
+  fence; \
 vtcode1 ## testnum: \
   add x2, x2, x3; \
   stop; \
@@ -664,8 +653,9 @@ handler ## testnum: \
   mfpcr a0, cr2; \
   li a1, aux; \
   bne a0, a1, fail; \
+  vsetcfg 32,0; \
   li a0,4; \
-  vvcfgivl a0,a0,32,0; \
+  vsetvl a0,a0; \
   la a0,src1; \
   la a1,src2; \
   vld vx2,a0; \
@@ -674,7 +664,7 @@ handler ## testnum: \
   vf %lo(vtcode2 ## testnum)(a0); \
   la a3,dest; \
   vsd vx2,a3; \
-  fence.v.l; \
+  fence; \
   ld a1,0(a3); \
   li a2,5; \
   li x28,2; \

diff --git a/isa/macros/vector/test_macros.h b/isa/macros/vector/test_macros.h
index 3a5d548f5e5888416201071ed2ee2b49bd68df29..6cfda128364602e032cabbeb9060814784b7f00d 100644 (file)
--- a/isa/macros/vector/test_macros.h
+++ b/isa/macros/vector/test_macros.h
@@ -13,13 +13,14 @@
 
 #define TEST_CASE_NREG( testnum, nxreg, nfreg, testreg, correctval, code... ) \
 test_ ## testnum: \
+  vsetcfg nxreg,nfreg; \
   li a3,2048; \
-  vvcfgivl a3,a3,nxreg,nfreg; \
+  vsetvl a3,a3; \
   lui a0,%hi(vtcode ## testnum ); \
   vf %lo(vtcode ## testnum )(a0); \
   la a4,dst; \
   vsd v ## testreg, a4; \
-  fence.v.l; \
+  fence; \
   li a1,correctval; \
   li a2,0; \
   li x28, testnum; \
@@ -216,8 +217,9 @@ next ## testnum :
 
 #define TEST_FP_OP_S_INTERNAL_NREG( testnum, nxreg, nfreg, result, val1, val2, val3, code... ) \
 test_ ## testnum: \
+  vsetcfg nxreg,nfreg; \
   li a3,2048; \
-  vvcfgivl a3,a3,nxreg,nfreg; \
+  vsetvl a3,a3; \
   la  a5, test_ ## testnum ## _data ;\
   vflstw vf0, a5, x0; \
   addi a5,a5,4; \
@@ -229,7 +231,7 @@ test_ ## testnum: \
   vf %lo(vtcode ## testnum )(a0); \
   la a4,dst; \
   vsw vx1, a4; \
-  fence.v.l; \
+  fence; \
   lw  a1, 0(a5); \
   li a2, 0; \
   li x28, testnum; \
@@ -255,8 +257,9 @@ vtcode ## testnum : \
 
 #define TEST_FP_OP_D_INTERNAL_NREG( testnum, nxreg, nfreg, result, val1, val2, val3, code... ) \
 test_ ## testnum: \
+  vsetcfg nxreg,nfreg; \
   li a3,2048; \
-  vvcfgivl a3,a3,nxreg,nfreg; \
+  vsetvl a3,a3; \
   la  a5, test_ ## testnum ## _data ;\
   vflstd vf0, a5, x0; \
   addi a5,a5,8; \
@@ -268,7 +271,7 @@ test_ ## testnum: \
   vf %lo(vtcode ## testnum )(a0); \
   la a4,dst; \
   vsd vx1, a4; \
-  fence.v.l; \
+  fence; \
   ld  a1, 0(a5); \
   li a2, 0; \
   li x28, testnum; \
@@ -334,13 +337,14 @@ vtcode ## testnum : \
 
 #define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
 test_ ## testnum: \
+  vsetcfg 2,1; \
   li a3,2048; \
-  vvcfgivl a3,a3,2,1; \
+  vsetvl a3,a3; \
   lui a0,%hi(vtcode ## testnum ); \
   vf %lo(vtcode ## testnum )(a0); \
   la a4,dst; \
   vsw vx1, a4; \
-  fence.v.l; \
+  fence; \
   la  a5, test_ ## testnum ## _data ;\
   lw  a1, 0(a5); \
   li a2, 0; \
@@ -366,13 +370,14 @@ vtcode ## testnum : \
 
 #define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
 test_ ## testnum: \
+  vsetcfg 2,1; \
   li a3,2048; \
-  vvcfgivl a3,a3,2,1; \
+  vsetvl a3,a3; \
   lui a0,%hi(vtcode ## testnum ); \
   vf %lo(vtcode ## testnum )(a0); \
   la a4,dst; \
   vsd vx1, a4; \
-  fence.v.l; \
+  fence; \
   la  a5, test_ ## testnum ## _data ;\
   ld  a1, 0(a5); \
   li a2, 0; \
@@ -515,12 +520,13 @@ vtcode ## testnum : \
 
 #define TEST_CASE_NREG_MEM( testnum, nxreg, nfreg, correctval, code... ) \
 test_ ## testnum: \
+  vsetcfg nxreg,nfreg; \
   li a3,2048; \
-  vvcfgivl a3,a3,nxreg,nfreg; \
+  vsetvl a3,a3; \
   lui a0,%hi(vtcode ## testnum ); \
   vf %lo(vtcode ## testnum )(a0); \
   la a4,dst; \
-  fence.v.l; \
+  fence; \
   li a1,correctval; \
   li a2,0; \
   li x28, testnum; \

diff --git a/isa/rv64sv/illegal_tvec_cmd.S b/isa/rv64sv/illegal_tvec_cmd.S
index d6d8d38cfb2986efc7061c03ddd4780b2a52626c..8943d860107a1f59a344dc191316f5ab01c845d1 100644 (file)
--- a/isa/rv64sv/illegal_tvec_cmd.S
+++ b/isa/rv64sv/illegal_tvec_cmd.S
@@ -20,8 +20,9 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3, dest+1
   vmsv vx1, a3
@@ -30,7 +31,7 @@ RVTEST_CODE_BEGIN
   venqcmd a3, x0
   lui a0,%hi(vtcode1)
   vf %lo(vtcode1)(a0)
-  fence.v.l
+  fence
 
 vtcode1:
   lw x2, 0(x1)
@@ -57,8 +58,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -68,7 +70,7 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5

diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
index d749104cda88dd5977589bc8b3cedd8d32e57add..d0e5574ee19067306add40296b99e117602688cd 100644 (file)
--- a/isa/rv64sv/illegal_vt_inst.S
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -20,8 +20,9 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -29,7 +30,7 @@ RVTEST_CODE_BEGIN
   vld vx3,a4
   lui a0,%hi(vtcode1)
   vf %lo(vtcode1)(a0)
-  fence.v.l
+  fence
 
 vtcode1:
   add x2,x2,x3
@@ -57,8 +58,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -68,7 +70,7 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5

diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
index a71c4a1baad5a82a9880a97094e0a07adcbcc83d..7b5db04ea61dd21bd677a280c0f1218e430e4d27 100644 (file)
--- a/isa/rv64sv/ma_utld.S
+++ b/isa/rv64sv/ma_utld.S
@@ -20,14 +20,15 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3, dest+1
   vmsv vx1, a3
   lui a0,%hi(vtcode1)
   vf %lo(vtcode1)(a0)
-  fence.v.l
+  fence
 
 vtcode1:
   lw x2, 0(x1)
@@ -53,8 +54,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -64,7 +66,7 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5

diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
index 6bdfcd559ab026d0d9b8072edc2487189ed10160..3b9e094a77746c88130ab6482484a57a9c610fa6 100644 (file)
--- a/isa/rv64sv/ma_utsd.S
+++ b/isa/rv64sv/ma_utsd.S
@@ -20,8 +20,9 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3, dest+1
   vmsv vx1, a3
@@ -29,7 +30,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode1)(a0)
   la a3, dest+1
   vsd vx1, a3
-  fence.v.l
+  fence
 
 vtcode1:
   sw x2, 0(x1)
@@ -55,8 +56,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -66,7 +68,7 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5

diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
index ef862c42e1e2b1356202656e0cb836c36b262e0d..bcf4b5af75bd1513db1d95b093f3053134ea6c87 100644 (file)
--- a/isa/rv64sv/ma_vld.S
+++ b/isa/rv64sv/ma_vld.S
@@ -20,15 +20,16 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3, dest+1
   vld vx2,a3
   vld vx3,a4
   lui a0,%hi(vtcode1)
   vf %lo(vtcode1)(a0)
-  fence.v.l
+  fence
 
 vtcode1:
   add x2,x2,x3
@@ -54,8 +55,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -65,7 +67,7 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5

diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S
index b82eb98715bdfaa2917b43debfbd48816f47fdec..682225053ddd1c025ad2613a09c29247829de1e3 100644 (file)
--- a/isa/rv64sv/ma_vsd.S
+++ b/isa/rv64sv/ma_vsd.S
@@ -20,8 +20,9 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3, src1
   la a4, src2
@@ -31,7 +32,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode1)(a0)
   la a3, dest+1
   vsd vx1, a3
-  fence.v.l
+  fence
 
 vtcode1:
   add x2,x2,x3
@@ -57,8 +58,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -68,7 +70,7 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5

diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index c8b7acba0f10b089b082c3a40eb32341a225b7d5..185924ce1cdbfad31a943e778b9a7d4ca660a01d 100644 (file)
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -20,8 +20,9 @@ RVTEST_CODE_BEGIN
   la a3,handler
   mtpcr a3,cr3 # set exception handler
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   lui a0,%hi(vtcode1+2)
   vf %lo(vtcode1+2)(a0)
@@ -47,8 +48,9 @@ handler:
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -58,7 +60,7 @@ handler:
   vf %lo(vtcode1)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5

diff --git a/isa/rv64uf/Makefrag b/isa/rv64uf/Makefrag
index 185a7990a00fb8012c3c4e3e2c29edb72c3b8304..5957d8d985722fd1279690c9b9704be5ff30db5e 100644 (file)
--- a/isa/rv64uf/Makefrag
+++ b/isa/rv64uf/Makefrag
@@ -15,4 +15,4 @@ rv64uf_p_vec_tests = $(addprefix rv64uf-p-vec-, $(rv64uf_sc_vec_tests))
 rv64uf_pt_vec_tests = $(addprefix rv64uf-pt-vec-, $(rv64uf_sc_vec_tests))
 rv64uf_v_vec_tests = $(addprefix rv64uf-v-vec-, $(rv64uf_sc_vec_tests))
 
-spike_tests += $(rv64uf_p_tests) #$(rv64uf_v_tests) $(rv64uf_p_vec_tests) $(rv64uf_pt_vec_tests) $(rv64uf_v_vec_tests)
+spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests) #$(rv64uf_p_vec_tests) $(rv64uf_pt_vec_tests) $(rv64uf_v_vec_tests)

diff --git a/isa/rv64uv/Makefrag b/isa/rv64uv/Makefrag
index dad31d2dd97ef7c1d77dfc47eadebfafc09ad612..955c27d92cdd321e18b15dcabca2d938d1bdf229 100644 (file)
--- a/isa/rv64uv/Makefrag
+++ b/isa/rv64uv/Makefrag
@@ -4,8 +4,8 @@
 
 rv64uv_sc_tests = \
        wakeup fence \
-       vvcfgivl vvcfg vsetvl \
-       vfmvv vmsv vmvv \
+       vsetcfgi vsetcfg vsetvl \
+       vmvv vmsv \
        utidx \
        lb lbu lh lhu lw lwu ld \
        sb sh sw sd \
@@ -31,4 +31,4 @@ rv64uv_p_vec_tests = $(addprefix rv64uv-p-vec-, $(rv64uv_sc_vec_tests))
 rv64uv_pt_vec_tests = $(addprefix rv64uv-pt-vec-, $(rv64uv_sc_vec_tests))
 rv64uv_v_vec_tests = $(addprefix rv64uv-v-vec-, $(rv64uv_sc_vec_tests))
 
-spike_tests += $(rv64uv_p_tests)
+spike_tests += #$(rv64uv_p_tests)

diff --git a/isa/rv64uv/amoadd_d.S b/isa/rv64uv/amoadd_d.S
index 053f7912f8b4ffc9084800926f2a2c507feb7569..ce3c6a6635364f1e6ef8e13f3b1047dca0acbe2c 100644 (file)
--- a/isa/rv64uv/amoadd_d.S
+++ b/isa/rv64uv/amoadd_d.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -22,7 +23,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
 loop:

diff --git a/isa/rv64uv/amoadd_w.S b/isa/rv64uv/amoadd_w.S
index cf006a79107ef8346b03650ee54312c52f9a495e..2bf010f5a86be0a242407f99fbbaec6a90cce04f 100644 (file)
--- a/isa/rv64uv/amoadd_w.S
+++ b/isa/rv64uv/amoadd_w.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -22,7 +23,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsw vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
 loop:

diff --git a/isa/rv64uv/amoand_d.S b/isa/rv64uv/amoand_d.S
index 5167ce661c7e529b56c61718ac00b60e8aed75f3..2652fbe8d08350f986ec582b587420750ff88cd6 100644 (file)
--- a/isa/rv64uv/amoand_d.S
+++ b/isa/rv64uv/amoand_d.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
   li a2,0

diff --git a/isa/rv64uv/amoand_w.S b/isa/rv64uv/amoand_w.S
index 111291bec4c71d6fe3336d4262003db3387ac0b8..93f660f53eccbe88125aff701d5abd79783bd81f 100644 (file)
--- a/isa/rv64uv/amoand_w.S
+++ b/isa/rv64uv/amoand_w.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsw vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
   li a2,0

diff --git a/isa/rv64uv/amomax_d.S b/isa/rv64uv/amomax_d.S
index e29e6e77280d866cba5da6efae15e4e03395435a..97a5cf4e25cfdb72de154cadd9d8245ae7b9adb7 100644 (file)
--- a/isa/rv64uv/amomax_d.S
+++ b/isa/rv64uv/amomax_d.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
   li a2,0

diff --git a/isa/rv64uv/amomax_w.S b/isa/rv64uv/amomax_w.S
index 2f7ebf4cf73124c173ed7b3c583ee709813666e9..f89bed6699bab28eaeb2d983ad0a500b0dc64d03 100644 (file)
--- a/isa/rv64uv/amomax_w.S
+++ b/isa/rv64uv/amomax_w.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsw vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
   li a2,0

diff --git a/isa/rv64uv/amomaxu_d.S b/isa/rv64uv/amomaxu_d.S
index 59a8a2860c9e8335b6e40215df5b0535d56e5732..679c04dae74bfc141853bf279f612e117915036f 100644 (file)
--- a/isa/rv64uv/amomaxu_d.S
+++ b/isa/rv64uv/amomaxu_d.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
   li a2,-1

diff --git a/isa/rv64uv/amomaxu_w.S b/isa/rv64uv/amomaxu_w.S
index 2a97c7158b9a04b7af127769b935f641a983e1d8..342d931c04e1fd8abbb2591b465546584b957a06 100644 (file)
--- a/isa/rv64uv/amomaxu_w.S
+++ b/isa/rv64uv/amomaxu_w.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsw vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
   li a2,-1

diff --git a/isa/rv64uv/amomin_d.S b/isa/rv64uv/amomin_d.S
index 01e1feb46b5695b5e62cdd8863eb937dc7b64d5d..c8dd43e6026c90572f129873a0af4b7beec0c425 100644 (file)
--- a/isa/rv64uv/amomin_d.S
+++ b/isa/rv64uv/amomin_d.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
   li a2,-1

diff --git a/isa/rv64uv/amomin_w.S b/isa/rv64uv/amomin_w.S
index bac8400048dc1af889eff84a889f1427d7ea0ef3..0633ba7a47243143c1c743a42829c15fa2b55a67 100644 (file)
--- a/isa/rv64uv/amomin_w.S
+++ b/isa/rv64uv/amomin_w.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsw vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
   li a2,0

diff --git a/isa/rv64uv/amominu_d.S b/isa/rv64uv/amominu_d.S
index 0951bab5da4276689dc84f229a6fc03e03779827..13fa5f22f9b58613d00ab007f1b8c1747c2e019d 100644 (file)
--- a/isa/rv64uv/amominu_d.S
+++ b/isa/rv64uv/amominu_d.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
   li a2,0

diff --git a/isa/rv64uv/amominu_w.S b/isa/rv64uv/amominu_w.S
index 67e5f93e738523f43413023943454eb578ba9b06..329b3549daf7e512ae66443191bb81909dc2561e 100644 (file)
--- a/isa/rv64uv/amominu_w.S
+++ b/isa/rv64uv/amominu_w.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsw vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
   li a2,0

diff --git a/isa/rv64uv/amoor_d.S b/isa/rv64uv/amoor_d.S
index b26f963c6206efe0f961d95b3b902a9a4e1a69fb..800550deea334f3460fa9d1ff5feb6c67868415d 100644 (file)
--- a/isa/rv64uv/amoor_d.S
+++ b/isa/rv64uv/amoor_d.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
   li a2,-1

diff --git a/isa/rv64uv/amoor_w.S b/isa/rv64uv/amoor_w.S
index 4d18c1007bb7e48be0237530cb36f144223acf94..cf8dcbf0299275149b001127be19d2272cb5ef6b 100644 (file)
--- a/isa/rv64uv/amoor_w.S
+++ b/isa/rv64uv/amoor_w.S
@@ -11,16 +11,14 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
-  la a5,amodest
-  vmsv vx2,a5
-  lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
   la a6,dest
   vsw vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
   li a2,-1

diff --git a/isa/rv64uv/amoswap_d.S b/isa/rv64uv/amoswap_d.S
index 0858277165392f554c4a6c55c9b66c38a8a39474..6a33b1f5fa06c82ba5d8ad0af0f7a2ecea336aa1 100644 (file)
--- a/isa/rv64uv/amoswap_d.S
+++ b/isa/rv64uv/amoswap_d.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
 loop:

diff --git a/isa/rv64uv/amoswap_w.S b/isa/rv64uv/amoswap_w.S
index ae6f1dac05032a54605c7149985d4787a3c9689c..3ba51cbfdf5e1dd60ba03702d99a79610964caa7 100644 (file)
--- a/isa/rv64uv/amoswap_w.S
+++ b/isa/rv64uv/amoswap_w.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsw vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
 loop:

diff --git a/isa/rv64uv/fcvt.S b/isa/rv64uv/fcvt.S
index 151e0543f1e88cda2aa90ea68a061283998729ad..180712f74de7bfff811bad720333bc7579af060d 100644 (file)
--- a/isa/rv64uv/fcvt.S
+++ b/isa/rv64uv/fcvt.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 32,32
   li a3,4
-  vvcfgivl a3,a3,32,32
+  vsetvl a3,a3
 
   la a3,src
   vld vx2,a3
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a4,dest
   vfsd vf0,a4
-  fence.v.l
+  fence
   la a5,result
   ld a1,0(a4)
   ld a2,0(a5)

diff --git a/isa/rv64uv/fence.S b/isa/rv64uv/fence.S
index 808fffad2705eeae1c8379f6e02b41d55a1947fd..7e9b90ede63e707c0e5ebed2d216aec6282e68e1 100644 (file)
--- a/isa/rv64uv/fence.S
+++ b/isa/rv64uv/fence.S
@@ -12,16 +12,21 @@ RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
   # make sure these don't choke at the beginning
-  fence.v.l
-  fence.v.g
+  fence
+  fence rw,io
+  fence io,rw
+  fence r,io
+  fence w,io
+  fence rw,i
+  fence rw,o
 
   li a0,1
   bne a0,x0,skip1
-  fence.v.l
+  fence
 skip1:
 
   bne a0,x0,skip3
-  fence.v.g
+  fence
 skip3:
 
   j pass

diff --git a/isa/rv64uv/fld.S b/isa/rv64uv/fld.S
index ab45100b60389f204b7bd9883c171ece3ea07b1c..c86fbc9ac8a7c41bfdd408601e209b5f5369cc8d 100644 (file)
--- a/isa/rv64uv/fld.S
+++ b/isa/rv64uv/fld.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,1
   li a4,512
-  vvcfgivl a4,a4,4,1
+  vsetvl a4,a4
 
   la a5,src
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vfsd vf0,a6
-  fence.v.l
+  fence
 
   li a2,0
 loop:

diff --git a/isa/rv64uv/flw.S b/isa/rv64uv/flw.S
index 0a42b7b131270b2ab56763b154d13b811204f54e..d9e6da4ab3bd325119d88b42c85def9e6ee23911 100644 (file)
--- a/isa/rv64uv/flw.S
+++ b/isa/rv64uv/flw.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,1
   li a4,2048
-  vvcfgivl a4,a4,4,1
+  vsetvl a4,a4
 
   la a5,src
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vfsw vf0,a6
-  fence.v.l
+  fence
 
   li a2,0
 loop:

diff --git a/isa/rv64uv/fma.S b/isa/rv64uv/fma.S
index eb56358b2275e49aff8b5113e935c2662b4af303..15a9c6a1114bfc979884c77bf467888a0d67eb6f 100644 (file)
--- a/isa/rv64uv/fma.S
+++ b/isa/rv64uv/fma.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 3,2
   li a3,2048
-  vvcfgivl a3,a3,3,2
+  vsetvl a3,a3
 
   la a4,src
   fld f0,0(a4)
@@ -35,7 +36,7 @@ wait:
 
   la a5,dest
   vfsd vf0,a5
-  fence.v.l
+  fence
 
   la s3,result
   ld s4,0(s3)

diff --git a/isa/rv64uv/fmovn.S b/isa/rv64uv/fmovn.S
index 1d6e87ee22ec3a22044511e90547fa5bc63908b4..a943326c5086eff00a4001993f3c70db4c4c12b2 100644 (file)
--- a/isa/rv64uv/fmovn.S
+++ b/isa/rv64uv/fmovn.S
@@ -11,14 +11,15 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,2
   li a6,2048
-  vvcfgivl a6,a6,4,2
+  vsetvl a6,a6
 
   lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
   la a7,dest
   vfsd vf0,a7
-  fence.v.l
+  fence
 
   li a1,0
   li a2,-1

diff --git a/isa/rv64uv/fmovz.S b/isa/rv64uv/fmovz.S
index 3090ac35049a302cacc09c96c5a2403e464260ad..9142cf0b92f4662bb6a13836f2909e7f800e8618 100644 (file)
--- a/isa/rv64uv/fmovz.S
+++ b/isa/rv64uv/fmovz.S
@@ -11,14 +11,15 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,2
   li a6,2048
-  vvcfgivl a6,a6,4,2
+  vsetvl a6,a6
 
   lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
   la a7,dest
   vfsd vf0,a7
-  fence.v.l
+  fence
 
   li a1,0
   li a2,-1

diff --git a/isa/rv64uv/fsd.S b/isa/rv64uv/fsd.S
index d85a5f7f11d8164085db6fbd568c61d25d749b5b..b6b60fece386f2cc5b5e9138984cda1ff1e7c0b0 100644 (file)
--- a/isa/rv64uv/fsd.S
+++ b/isa/rv64uv/fsd.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,1
   li a4,2048
-  vvcfgivl a4,a4,4,1
+  vsetvl a4,a4
 
   la a5,src
   vfld vf0,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vmsv vx2,a6
   lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
-  fence.v.l
+  fence
 
   li a2,0
 loop:

diff --git a/isa/rv64uv/fsw.S b/isa/rv64uv/fsw.S
index 69702d0bc775b10219903199f4ba67f20385e7b8..eaafeff4bc4a92b3fc5d1fe0b9399f9ea5a66afd 100644 (file)
--- a/isa/rv64uv/fsw.S
+++ b/isa/rv64uv/fsw.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,1
   li a4,2048
-  vvcfgivl a4,a4,4,1
+  vsetvl a4,a4
 
   la a5,src
   vflw vf0,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vmsv vx2,a6
   lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
-  fence.v.l
+  fence
 
   li a2,0
 loop:

diff --git a/isa/rv64uv/imul.S b/isa/rv64uv/imul.S
index bb9b6a36c4215834ec28369a822358d7e540374b..0925e59de724db46b6c513e83dab2898bc8ebe67 100644 (file)
--- a/isa/rv64uv/imul.S
+++ b/isa/rv64uv/imul.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 3,0
   li a3,2048
-  vvcfgivl a3,a3,3,0
+  vsetvl a3,a3
 
   li a4,20
   li s0,2
@@ -44,7 +45,7 @@ RVTEST_CODE_BEGIN
 
   la a5,dest
   vsd vx1,a5
-  fence.v.l
+  fence
 
   li s2,40
   li x28,2

diff --git a/isa/rv64uv/lb.S b/isa/rv64uv/lb.S
index 24c7caaf866bcede84b0762d87236d91fecc7c0b..7e20b65ccd3efdec5690fb21cc070f0a8307213b 100644 (file)
--- a/isa/rv64uv/lb.S
+++ b/isa/rv64uv/lb.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 16,0
   li a4,512
-  vvcfgivl a4,a4,16,0
+  vsetvl a4,a4
 
   la a5,src
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a2,0
 loop:

diff --git a/isa/rv64uv/lbu.S b/isa/rv64uv/lbu.S
index 7fce7525d5ab9dff9bbc1cead9bab03df95651b5..166f40e7f8b754f04c82f161c8151d3ec6710120 100644 (file)
--- a/isa/rv64uv/lbu.S
+++ b/isa/rv64uv/lbu.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 16,0
   li a4,512
-  vvcfgivl a4,a4,16,0
+  vsetvl a4,a4
 
   la a5,src
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a2,0
 loop:

diff --git a/isa/rv64uv/ld.S b/isa/rv64uv/ld.S
index 03303b400904d06ad52521881d5e4ede62bea29a..a2f6b891d19bda5becd234b0e4cbd97fa8869990 100644 (file)
--- a/isa/rv64uv/ld.S
+++ b/isa/rv64uv/ld.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 16,0
   li a4,512
-  vvcfgivl a4,a4,16,0
+  vsetvl a4,a4
 
   la a5,src
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a2,0
 loop:

diff --git a/isa/rv64uv/lh.S b/isa/rv64uv/lh.S
index 98b001c464aac728ba023783f74bb1e39487ad77..910ffd35a877c056ffec82668a48dca933958995 100644 (file)
--- a/isa/rv64uv/lh.S
+++ b/isa/rv64uv/lh.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 16,0
   li a4,512
-  vvcfgivl a4,a4,16,0
+  vsetvl a4,a4
 
   la a5,src
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a2,0
 loop:

diff --git a/isa/rv64uv/lhu.S b/isa/rv64uv/lhu.S
index caa2c1cfaac3702b8368827032c4a248053f34a8..7d4fb5ab097dab0bfc167362b87505c71bdc1f0c 100644 (file)
--- a/isa/rv64uv/lhu.S
+++ b/isa/rv64uv/lhu.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 16,0
   li a4,512
-  vvcfgivl a4,a4,16,0
+  vsetvl a4,a4
 
   la a5,src
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a2,0
 loop:

diff --git a/isa/rv64uv/lw.S b/isa/rv64uv/lw.S
index 5576bc61fb0efc57cbc0b1c4d6a46b02fdfcf283..8b1563645d931c18d418562b35339cdd866f6d76 100644 (file)
--- a/isa/rv64uv/lw.S
+++ b/isa/rv64uv/lw.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 16,0
   li a4,512
-  vvcfgivl a4,a4,16,0
+  vsetvl a4,a4
 
   la a5,src
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a2,0
 loop:

diff --git a/isa/rv64uv/lwu.S b/isa/rv64uv/lwu.S
index d8b5bf2e62b91af22d08228f067ee7c761831b37..6cbb30276610c08d3b2c7af43548ff834278730b 100644 (file)
--- a/isa/rv64uv/lwu.S
+++ b/isa/rv64uv/lwu.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 16,0
   li a4,512
-  vvcfgivl a4,a4,16,0
+  vsetvl a4,a4
 
   la a5,src
   vmsv vx2,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsd vx1,a6
-  fence.v.l
+  fence
 
   li a2,0
 loop:

diff --git a/isa/rv64uv/movn.S b/isa/rv64uv/movn.S
index 91a5a3c7adc29c8f6938d8bf6941ef056b021d0b..84bb27ef25d5ecde4e7a08b190e5e0b33c289a2a 100644 (file)
--- a/isa/rv64uv/movn.S
+++ b/isa/rv64uv/movn.S
@@ -11,14 +11,15 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a6,2048
-  vvcfgivl a6,a6,4,0
+  vsetvl a6,a6
 
   lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
   la a7,dest
   vsd vx3,a7
-  fence.v.l
+  fence
 
   li a1,0
   li a2,-1

diff --git a/isa/rv64uv/movz.S b/isa/rv64uv/movz.S
index 683afdb6f89f249460eb42e59db55ef3122533e8..93328116516c74592d77f31458751cade1ea2eaf 100644 (file)
--- a/isa/rv64uv/movz.S
+++ b/isa/rv64uv/movz.S
@@ -11,14 +11,15 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a6,2048
-  vvcfgivl a6,a6,4,0
+  vsetvl a6,a6
 
   lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
   la a7,dest
   vsd vx3,a7
-  fence.v.l
+  fence
 
   li a1,0
   li a2,-1

diff --git a/isa/rv64uv/sb.S b/isa/rv64uv/sb.S
index bcee091e8811a825406137eb867b06a2dba8e3c8..9155de9a1584f9836e1f08520e05f74ea5798f12 100644 (file)
--- a/isa/rv64uv/sb.S
+++ b/isa/rv64uv/sb.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 16,0
   li a4,512
-  vvcfgivl a4,a4,16,0
+  vsetvl a4,a4
 
   la a6,dest
   li a2,0
@@ -30,7 +31,7 @@ initloop:
   vmsv vx2,a6
   lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
-  fence.v.l
+  fence
 
   li a2,0
 loop:

diff --git a/isa/rv64uv/sd.S b/isa/rv64uv/sd.S
index dd6f72ae424e87db7a25013e3513071aeb2ade46..67b336c0165cad62981a0294b6649d45c43314aa 100644 (file)
--- a/isa/rv64uv/sd.S
+++ b/isa/rv64uv/sd.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 16,0
   li a4,512
-  vvcfgivl a4,a4,16,0
+  vsetvl a4,a4
 
   la a5,src
   vld vx1,a5
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vmsv vx2,a6
   lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
-  fence.v.l
+  fence
 
   li a2,0
 loop:

diff --git a/isa/rv64uv/sh.S b/isa/rv64uv/sh.S
index 6dc5ab8c141441bb90fe7642ac0985b14f9e98a3..e35a77b2ea552bad4164c2ab53a0e0c9ef6a6c43 100644 (file)
--- a/isa/rv64uv/sh.S
+++ b/isa/rv64uv/sh.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 16,0
   li a4,512
-  vvcfgivl a4,a4,16,0
+  vsetvl a4,a4
 
   la a6,dest
   li a2,0
@@ -30,7 +31,7 @@ initloop:
   vmsv vx2,a6
   lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
-  fence.v.l
+  fence
 
   li a2,0
 loop:

diff --git a/isa/rv64uv/sw.S b/isa/rv64uv/sw.S
index 985e12a22b74bd728e589fc0f2d80d253ac1f5a9..6f883ffe219816debbfd39347e1dd79c23e954d2 100644 (file)
--- a/isa/rv64uv/sw.S
+++ b/isa/rv64uv/sw.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 16,0
   li a4,512
-  vvcfgivl a4,a4,16,0
+  vsetvl a4,a4
 
   la a6,dest
   li a2,0
@@ -30,7 +31,7 @@ initloop:
   vmsv vx2,a6
   lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
-  fence.v.l
+  fence
 
   li a2,0
 loop:

diff --git a/isa/rv64uv/utidx.S b/isa/rv64uv/utidx.S
index 95d954c56487a75f2287d05bcad1b1a4c7cdd96a..7de7a20c7c3a722eda106e6dbf16cbf6d876550f 100644 (file)
--- a/isa/rv64uv/utidx.S
+++ b/isa/rv64uv/utidx.S
@@ -11,14 +11,15 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 2,0
   li a2,2048
-  vvcfgivl a2,a2,2,0
+  vsetvl a2,a2
 
   lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
   la a4,dest
   vsd vx1,a4
-  fence.v.l
+  fence
 
   li a1,1
 loop:

diff --git a/isa/rv64uv/vfmvv.S b/isa/rv64uv/vfmvv.S
index 2f6e8bf084a426b5f784270aa272fd74aa1e26ff..6154620b8762a9eca2edf43689edcd72485157a2 100644 (file)
--- a/isa/rv64uv/vfmvv.S
+++ b/isa/rv64uv/vfmvv.S
@@ -11,15 +11,16 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 2,2
   li a2,2048
-  vvcfgivl a2,a2,2,2
+  vsetvl a2,a2
 
   lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
   vfmvv vf1,vf0
   la a3,dest
   vfsd vf1,a3
-  fence.v.l
+  fence
 
   li a1,1
 loop:

diff --git a/isa/rv64uv/vmsv.S b/isa/rv64uv/vmsv.S
index 732f66014c1f31fcefbb8638d2efa885fc57c243..b66288c23ea18e77d953d8f1ef6f99a112017075 100644 (file)
--- a/isa/rv64uv/vmsv.S
+++ b/isa/rv64uv/vmsv.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 3,0
   li a2,2048
-  vvcfgivl a2,a2,3,0
+  vsetvl a2,a2
 
   li a3,-1
   vmsv vx2,a3
@@ -20,7 +21,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a4,dest
   vsd vx2,a4
-  fence.v.l
+  fence
 
   li a1,0
 loop:

diff --git a/isa/rv64uv/vmvv.S b/isa/rv64uv/vmvv.S
index 17e5865bbc4185f85a588391be1f4cfab0b6f969..3b316b96a222ed79d01982040d6363636efa8f2a 100644 (file)
--- a/isa/rv64uv/vmvv.S
+++ b/isa/rv64uv/vmvv.S
@@ -11,15 +11,16 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 3,0
   li a2,2048
-  vvcfgivl a2,a2,3,0
+  vsetvl a2,a2
 
   lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
   vmvv vx2,vx1
   la a4,dest
   vsd vx2,a4
-  fence.v.l
+  fence
 
   li a1,1
 loop:

diff --git a/isa/rv64uv/vsetcfg.S b/isa/rv64uv/vsetcfg.S
new file mode 100644 (file)
index 0000000..9aed298
--- /dev/null
+++ b/isa/rv64uv/vsetcfg.S
@@ -0,0 +1,559 @@
+#*****************************************************************************
+# vsetcfg.S
+#-----------------------------------------------------------------------------
+#
+# Test vsetcfg instruction without immediates.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_VVCFG( 2, 0, 0, 0xf8, 768, 768 );
+  TEST_VVCFG( 3, 0, 0, 0xf8, 769, 768 );
+  TEST_VVCFG( 4, 0, 0, 0xf8, 767, 767 );
+
+  TEST_VVCFG( 5, 0, 0, 0x00, 2048, 2048 );
+  TEST_VVCFG( 6, 0, 0, 0x00, 2049, 2048 );
+  TEST_VVCFG( 7, 0, 0, 0x00, 2047, 2047 );
+
+  TEST_VVCFG( 8, 1, 0, 0xf8, 768, 768 );
+  TEST_VVCFG( 9, 1, 0, 0xf8, 769, 768 );
+  TEST_VVCFG( 10, 1, 0, 0xf8, 767, 767 );
+
+  TEST_VVCFG( 11, 1, 0, 0x00, 2048, 2048 );
+  TEST_VVCFG( 12, 1, 0, 0x00, 2049, 2048 );
+  TEST_VVCFG( 13, 1, 0, 0x00, 2047, 2047 );
+
+  TEST_VVCFG( 14, 2, 0, 0xf8, 768, 768 );
+  TEST_VVCFG( 15, 2, 0, 0xf8, 769, 768 );
+  TEST_VVCFG( 16, 2, 0, 0xf8, 767, 767 );
+
+  TEST_VVCFG( 17, 2, 0, 0x00, 2048, 2048 );
+  TEST_VVCFG( 18, 2, 0, 0x00, 2049, 2048 );
+  TEST_VVCFG( 19, 2, 0, 0x00, 2047, 2047 );
+
+  TEST_VVCFG( 20, 3, 0, 0xf8, 384, 384 );
+  TEST_VVCFG( 21, 3, 0, 0xf8, 385, 384 );
+  TEST_VVCFG( 22, 3, 0, 0xf8, 383, 383 );
+
+  TEST_VVCFG( 23, 3, 0, 0x00, 1024, 1024 );
+  TEST_VVCFG( 24, 3, 0, 0x00, 1025, 1024 );
+  TEST_VVCFG( 25, 3, 0, 0x00, 1023, 1023 );
+
+  TEST_VVCFG( 26, 4, 0, 0xf8, 255, 255 );
+  TEST_VVCFG( 27, 4, 0, 0xf8, 256, 255 );
+  TEST_VVCFG( 28, 4, 0, 0xf8, 254, 254 );
+
+  TEST_VVCFG( 29, 4, 0, 0x00, 680, 680 );
+  TEST_VVCFG( 30, 4, 0, 0x00, 681, 680 );
+  TEST_VVCFG( 31, 4, 0, 0x00, 679, 679 );
+
+  TEST_VVCFG( 32, 5, 0, 0xf8, 192, 192 );
+  TEST_VVCFG( 33, 5, 0, 0xf8, 193, 192 );
+  TEST_VVCFG( 34, 5, 0, 0xf8, 191, 191 );
+
+  TEST_VVCFG( 35, 5, 0, 0x00, 512, 512 );
+  TEST_VVCFG( 36, 5, 0, 0x00, 513, 512 );
+  TEST_VVCFG( 37, 5, 0, 0x00, 511, 511 );
+
+  TEST_VVCFG( 38, 6, 0, 0xf8, 153, 153 );
+  TEST_VVCFG( 39, 6, 0, 0xf8, 154, 153 );
+  TEST_VVCFG( 40, 6, 0, 0xf8, 152, 152 );
+
+  TEST_VVCFG( 41, 6, 0, 0x00, 408, 408 );
+  TEST_VVCFG( 42, 6, 0, 0x00, 409, 408 );
+  TEST_VVCFG( 43, 6, 0, 0x00, 407, 407 );
+
+  TEST_VVCFG( 44, 7, 0, 0xf8, 126, 126 );
+  TEST_VVCFG( 45, 7, 0, 0xf8, 127, 126 );
+  TEST_VVCFG( 46, 7, 0, 0xf8, 125, 125 );
+
+  TEST_VVCFG( 47, 7, 0, 0x00, 336, 336 );
+  TEST_VVCFG( 48, 7, 0, 0x00, 337, 336 );
+  TEST_VVCFG( 49, 7, 0, 0x00, 335, 335 );
+
+  TEST_VVCFG( 50, 8, 0, 0xf8, 108, 108 );
+  TEST_VVCFG( 51, 8, 0, 0xf8, 109, 108 );
+  TEST_VVCFG( 52, 8, 0, 0xf8, 107, 107 );
+
+  TEST_VVCFG( 53, 8, 0, 0x00, 288, 288 );
+  TEST_VVCFG( 54, 8, 0, 0x00, 289, 288 );
+  TEST_VVCFG( 55, 8, 0, 0x00, 287, 287 );
+
+  TEST_VVCFG( 56, 9, 0, 0xf8, 96, 96 );
+  TEST_VVCFG( 57, 9, 0, 0xf8, 97, 96 );
+  TEST_VVCFG( 58, 9, 0, 0xf8, 95, 95 );
+
+  TEST_VVCFG( 59, 9, 0, 0x00, 256, 256 );
+  TEST_VVCFG( 60, 9, 0, 0x00, 257, 256 );
+  TEST_VVCFG( 61, 9, 0, 0x00, 255, 255 );
+
+  TEST_VVCFG( 62, 10, 0, 0xf8, 84, 84 );
+  TEST_VVCFG( 63, 10, 0, 0xf8, 85, 84 );
+  TEST_VVCFG( 64, 10, 0, 0xf8, 83, 83 );
+
+  TEST_VVCFG( 65, 10, 0, 0x00, 224, 224 );
+  TEST_VVCFG( 66, 10, 0, 0x00, 225, 224 );
+  TEST_VVCFG( 67, 10, 0, 0x00, 223, 223 );
+
+  TEST_VVCFG( 68, 11, 0, 0xf8, 75, 75 );
+  TEST_VVCFG( 69, 11, 0, 0xf8, 76, 75 );
+  TEST_VVCFG( 70, 11, 0, 0xf8, 74, 74 );
+
+  TEST_VVCFG( 71, 11, 0, 0x00, 200, 200 );
+  TEST_VVCFG( 72, 11, 0, 0x00, 201, 200 );
+  TEST_VVCFG( 73, 11, 0, 0x00, 199, 199 );
+
+  TEST_VVCFG( 74, 12, 0, 0xf8, 69, 69 );
+  TEST_VVCFG( 75, 12, 0, 0xf8, 70, 69 );
+  TEST_VVCFG( 76, 12, 0, 0xf8, 68, 68 );
+
+  TEST_VVCFG( 77, 12, 0, 0x00, 184, 184 );
+  TEST_VVCFG( 78, 12, 0, 0x00, 185, 184 );
+  TEST_VVCFG( 79, 12, 0, 0x00, 183, 183 );
+
+  TEST_VVCFG( 80, 13, 0, 0xf8, 63, 63 );
+  TEST_VVCFG( 81, 13, 0, 0xf8, 64, 63 );
+  TEST_VVCFG( 82, 13, 0, 0xf8, 62, 62 );
+
+  TEST_VVCFG( 83, 13, 0, 0x00, 168, 168 );
+  TEST_VVCFG( 84, 13, 0, 0x00, 169, 168 );
+  TEST_VVCFG( 85, 13, 0, 0x00, 167, 167 );
+
+  TEST_VVCFG( 86, 14, 0, 0xf8, 57, 57 );
+  TEST_VVCFG( 87, 14, 0, 0xf8, 58, 57 );
+  TEST_VVCFG( 88, 14, 0, 0xf8, 56, 56 );
+
+  TEST_VVCFG( 89, 14, 0, 0x00, 152, 152 );
+  TEST_VVCFG( 90, 14, 0, 0x00, 153, 152 );
+  TEST_VVCFG( 91, 14, 0, 0x00, 151, 151 );
+
+  TEST_VVCFG( 92, 15, 0, 0xf8, 54, 54 );
+  TEST_VVCFG( 93, 15, 0, 0xf8, 55, 54 );
+  TEST_VVCFG( 94, 15, 0, 0xf8, 53, 53 );
+
+  TEST_VVCFG( 95, 15, 0, 0x00, 144, 144 );
+  TEST_VVCFG( 96, 15, 0, 0x00, 145, 144 );
+  TEST_VVCFG( 97, 15, 0, 0x00, 143, 143 );
+
+  TEST_VVCFG( 98, 16, 0, 0xf8, 51, 51 );
+  TEST_VVCFG( 99, 16, 0, 0xf8, 52, 51 );
+  TEST_VVCFG( 100, 16, 0, 0xf8, 50, 50 );
+
+  TEST_VVCFG( 101, 16, 0, 0x00, 136, 136 );
+  TEST_VVCFG( 102, 16, 0, 0x00, 137, 136 );
+  TEST_VVCFG( 103, 16, 0, 0x00, 135, 135 );
+
+  TEST_VVCFG( 104, 17, 0, 0xf8, 48, 48 );
+  TEST_VVCFG( 105, 17, 0, 0xf8, 49, 48 );
+  TEST_VVCFG( 106, 17, 0, 0xf8, 47, 47 );
+
+  TEST_VVCFG( 107, 17, 0, 0x00, 128, 128 );
+  TEST_VVCFG( 108, 17, 0, 0x00, 129, 128 );
+  TEST_VVCFG( 109, 17, 0, 0x00, 127, 127 );
+
+  TEST_VVCFG( 110, 18, 0, 0xf8, 45, 45 );
+  TEST_VVCFG( 111, 18, 0, 0xf8, 46, 45 );
+  TEST_VVCFG( 112, 18, 0, 0xf8, 44, 44 );
+
+  TEST_VVCFG( 113, 18, 0, 0x00, 120, 120 );
+  TEST_VVCFG( 114, 18, 0, 0x00, 121, 120 );
+  TEST_VVCFG( 115, 18, 0, 0x00, 119, 119 );
+
+  TEST_VVCFG( 116, 19, 0, 0xf8, 42, 42 );
+  TEST_VVCFG( 117, 19, 0, 0xf8, 43, 42 );
+  TEST_VVCFG( 118, 19, 0, 0xf8, 41, 41 );
+
+  TEST_VVCFG( 119, 19, 0, 0x00, 112, 112 );
+  TEST_VVCFG( 120, 19, 0, 0x00, 113, 112 );
+  TEST_VVCFG( 121, 19, 0, 0x00, 111, 111 );
+
+  TEST_VVCFG( 122, 20, 0, 0xf8, 39, 39 );
+  TEST_VVCFG( 123, 20, 0, 0xf8, 40, 39 );
+  TEST_VVCFG( 124, 20, 0, 0xf8, 38, 38 );
+
+  TEST_VVCFG( 125, 20, 0, 0x00, 104, 104 );
+  TEST_VVCFG( 126, 20, 0, 0x00, 105, 104 );
+  TEST_VVCFG( 127, 20, 0, 0x00, 103, 103 );
+
+  TEST_VVCFG( 128, 21, 0, 0xf8, 36, 36 );
+  TEST_VVCFG( 129, 21, 0, 0xf8, 37, 36 );
+  TEST_VVCFG( 130, 21, 0, 0xf8, 35, 35 );
+
+  TEST_VVCFG( 131, 21, 0, 0x00, 96, 96 );
+  TEST_VVCFG( 132, 21, 0, 0x00, 97, 96 );
+  TEST_VVCFG( 133, 21, 0, 0x00, 95, 95 );
+
+  TEST_VVCFG( 134, 22, 0, 0xf8, 36, 36 );
+  TEST_VVCFG( 135, 22, 0, 0xf8, 37, 36 );
+  TEST_VVCFG( 136, 22, 0, 0xf8, 35, 35 );
+
+  TEST_VVCFG( 137, 22, 0, 0x00, 96, 96 );
+  TEST_VVCFG( 138, 22, 0, 0x00, 97, 96 );
+  TEST_VVCFG( 139, 22, 0, 0x00, 95, 95 );
+
+  TEST_VVCFG( 140, 23, 0, 0xf8, 33, 33 );
+  TEST_VVCFG( 141, 23, 0, 0xf8, 34, 33 );
+  TEST_VVCFG( 142, 23, 0, 0xf8, 32, 32 );
+
+  TEST_VVCFG( 143, 23, 0, 0x00, 88, 88 );
+  TEST_VVCFG( 144, 23, 0, 0x00, 89, 88 );
+  TEST_VVCFG( 145, 23, 0, 0x00, 87, 87 );
+
+  TEST_VVCFG( 146, 24, 0, 0xf8, 33, 33 );
+  TEST_VVCFG( 147, 24, 0, 0xf8, 34, 33 );
+  TEST_VVCFG( 148, 24, 0, 0xf8, 32, 32 );
+
+  TEST_VVCFG( 149, 24, 0, 0x00, 88, 88 );
+  TEST_VVCFG( 150, 24, 0, 0x00, 89, 88 );
+  TEST_VVCFG( 151, 24, 0, 0x00, 87, 87 );
+
+  TEST_VVCFG( 152, 25, 0, 0xf8, 30, 30 );
+  TEST_VVCFG( 153, 25, 0, 0xf8, 31, 30 );
+  TEST_VVCFG( 154, 25, 0, 0xf8, 29, 29 );
+
+  TEST_VVCFG( 155, 25, 0, 0x00, 80, 80 );
+  TEST_VVCFG( 156, 25, 0, 0x00, 81, 80 );
+  TEST_VVCFG( 157, 25, 0, 0x00, 79, 79 );
+
+  TEST_VVCFG( 158, 26, 0, 0xf8, 30, 30 );
+  TEST_VVCFG( 159, 26, 0, 0xf8, 31, 30 );
+  TEST_VVCFG( 160, 26, 0, 0xf8, 29, 29 );
+
+  TEST_VVCFG( 161, 26, 0, 0x00, 80, 80 );
+  TEST_VVCFG( 162, 26, 0, 0x00, 81, 80 );
+  TEST_VVCFG( 163, 26, 0, 0x00, 79, 79 );
+
+  TEST_VVCFG( 164, 27, 0, 0xf8, 27, 27 );
+  TEST_VVCFG( 165, 27, 0, 0xf8, 28, 27 );
+  TEST_VVCFG( 166, 27, 0, 0xf8, 26, 26 );
+
+  TEST_VVCFG( 167, 27, 0, 0x00, 72, 72 );
+  TEST_VVCFG( 168, 27, 0, 0x00, 73, 72 );
+  TEST_VVCFG( 169, 27, 0, 0x00, 71, 71 );
+
+  TEST_VVCFG( 170, 28, 0, 0xf8, 27, 27 );
+  TEST_VVCFG( 171, 28, 0, 0xf8, 28, 27 );
+  TEST_VVCFG( 172, 28, 0, 0xf8, 26, 26 );
+
+  TEST_VVCFG( 173, 28, 0, 0x00, 72, 72 );
+  TEST_VVCFG( 174, 28, 0, 0x00, 73, 72 );
+  TEST_VVCFG( 175, 28, 0, 0x00, 71, 71 );
+
+  TEST_VVCFG( 176, 29, 0, 0xf8, 27, 27 );
+  TEST_VVCFG( 177, 29, 0, 0xf8, 28, 27 );
+  TEST_VVCFG( 178, 29, 0, 0xf8, 26, 26 );
+
+  TEST_VVCFG( 179, 29, 0, 0x00, 72, 72 );
+  TEST_VVCFG( 180, 29, 0, 0x00, 73, 72 );
+  TEST_VVCFG( 181, 29, 0, 0x00, 71, 71 );
+
+  TEST_VVCFG( 182, 30, 0, 0xf8, 24, 24 );
+  TEST_VVCFG( 183, 30, 0, 0xf8, 25, 24 );
+  TEST_VVCFG( 184, 30, 0, 0xf8, 23, 23 );
+
+  TEST_VVCFG( 185, 30, 0, 0x00, 64, 64 );
+  TEST_VVCFG( 186, 30, 0, 0x00, 65, 64 );
+  TEST_VVCFG( 187, 30, 0, 0x00, 63, 63 );
+
+  TEST_VVCFG( 188, 31, 0, 0xf8, 24, 24 );
+  TEST_VVCFG( 189, 31, 0, 0xf8, 25, 24 );
+  TEST_VVCFG( 190, 31, 0, 0xf8, 23, 23 );
+
+  TEST_VVCFG( 191, 31, 0, 0x00, 64, 64 );
+  TEST_VVCFG( 192, 31, 0, 0x00, 65, 64 );
+  TEST_VVCFG( 193, 31, 0, 0x00, 63, 63 );
+
+  TEST_VVCFG( 194, 32, 0, 0xf8, 24, 24 );
+  TEST_VVCFG( 195, 32, 0, 0xf8, 25, 24 );
+  TEST_VVCFG( 196, 32, 0, 0xf8, 23, 23 );
+
+  TEST_VVCFG( 197, 32, 0, 0x00, 64, 64 );
+  TEST_VVCFG( 198, 32, 0, 0x00, 65, 64 );
+  TEST_VVCFG( 199, 32, 0, 0x00, 63, 63 );
+
+  TEST_VVCFG( 200, 32, 0, 0xf8, 24, 24 );
+  TEST_VVCFG( 201, 32, 0, 0xf8, 25, 24 );
+  TEST_VVCFG( 202, 32, 0, 0xf8, 23, 23 );
+
+  TEST_VVCFG( 203, 32, 0, 0x00, 64, 64 );
+  TEST_VVCFG( 204, 32, 0, 0x00, 65, 64 );
+  TEST_VVCFG( 205, 32, 0, 0x00, 63, 63 );
+
+  TEST_VVCFG( 206, 32, 1, 0xf8, 24, 24 );
+  TEST_VVCFG( 207, 32, 1, 0xf8, 25, 24 );
+  TEST_VVCFG( 208, 32, 1, 0xf8, 23, 23 );
+
+  TEST_VVCFG( 209, 32, 1, 0x00, 64, 64 );
+  TEST_VVCFG( 210, 32, 1, 0x00, 65, 64 );
+  TEST_VVCFG( 211, 32, 1, 0x00, 63, 63 );
+
+  TEST_VVCFG( 212, 32, 2, 0xf8, 21, 21 );
+  TEST_VVCFG( 213, 32, 2, 0xf8, 22, 21 );
+  TEST_VVCFG( 214, 32, 2, 0xf8, 20, 20 );
+
+  TEST_VVCFG( 215, 32, 2, 0x00, 56, 56 );
+  TEST_VVCFG( 216, 32, 2, 0x00, 57, 56 );
+  TEST_VVCFG( 217, 32, 2, 0x00, 55, 55 );
+
+  TEST_VVCFG( 218, 32, 3, 0xf8, 21, 21 );
+  TEST_VVCFG( 219, 32, 3, 0xf8, 22, 21 );
+  TEST_VVCFG( 220, 32, 3, 0xf8, 20, 20 );
+
+  TEST_VVCFG( 221, 32, 3, 0x00, 56, 56 );
+  TEST_VVCFG( 222, 32, 3, 0x00, 57, 56 );
+  TEST_VVCFG( 223, 32, 3, 0x00, 55, 55 );
+
+  TEST_VVCFG( 224, 32, 4, 0xf8, 21, 21 );
+  TEST_VVCFG( 225, 32, 4, 0xf8, 22, 21 );
+  TEST_VVCFG( 226, 32, 4, 0xf8, 20, 20 );
+
+  TEST_VVCFG( 227, 32, 4, 0x00, 56, 56 );
+  TEST_VVCFG( 228, 32, 4, 0x00, 57, 56 );
+  TEST_VVCFG( 229, 32, 4, 0x00, 55, 55 );
+
+  TEST_VVCFG( 230, 32, 5, 0xf8, 21, 21 );
+  TEST_VVCFG( 231, 32, 5, 0xf8, 22, 21 );
+  TEST_VVCFG( 232, 32, 5, 0xf8, 20, 20 );
+
+  TEST_VVCFG( 233, 32, 5, 0x00, 56, 56 );
+  TEST_VVCFG( 234, 32, 5, 0x00, 57, 56 );
+  TEST_VVCFG( 235, 32, 5, 0x00, 55, 55 );
+
+  TEST_VVCFG( 236, 32, 6, 0xf8, 18, 18 );
+  TEST_VVCFG( 237, 32, 6, 0xf8, 19, 18 );
+  TEST_VVCFG( 238, 32, 6, 0xf8, 17, 17 );
+
+  TEST_VVCFG( 239, 32, 6, 0x00, 48, 48 );
+  TEST_VVCFG( 240, 32, 6, 0x00, 49, 48 );
+  TEST_VVCFG( 241, 32, 6, 0x00, 47, 47 );
+
+  TEST_VVCFG( 242, 32, 7, 0xf8, 18, 18 );
+  TEST_VVCFG( 243, 32, 7, 0xf8, 19, 18 );
+  TEST_VVCFG( 244, 32, 7, 0xf8, 17, 17 );
+
+  TEST_VVCFG( 245, 32, 7, 0x00, 48, 48 );
+  TEST_VVCFG( 246, 32, 7, 0x00, 49, 48 );
+  TEST_VVCFG( 247, 32, 7, 0x00, 47, 47 );
+
+  TEST_VVCFG( 248, 32, 8, 0xf8, 18, 18 );
+  TEST_VVCFG( 249, 32, 8, 0xf8, 19, 18 );
+  TEST_VVCFG( 250, 32, 8, 0xf8, 17, 17 );
+
+  TEST_VVCFG( 251, 32, 8, 0x00, 48, 48 );
+  TEST_VVCFG( 252, 32, 8, 0x00, 49, 48 );
+  TEST_VVCFG( 253, 32, 8, 0x00, 47, 47 );
+
+  TEST_VVCFG( 254, 32, 9, 0xf8, 18, 18 );
+  TEST_VVCFG( 255, 32, 9, 0xf8, 19, 18 );
+  TEST_VVCFG( 256, 32, 9, 0xf8, 17, 17 );
+
+  TEST_VVCFG( 257, 32, 9, 0x00, 48, 48 );
+  TEST_VVCFG( 258, 32, 9, 0x00, 49, 48 );
+  TEST_VVCFG( 259, 32, 9, 0x00, 47, 47 );
+
+  TEST_VVCFG( 260, 32, 10, 0xf8, 18, 18 );
+  TEST_VVCFG( 261, 32, 10, 0xf8, 19, 18 );
+  TEST_VVCFG( 262, 32, 10, 0xf8, 17, 17 );
+
+  TEST_VVCFG( 263, 32, 10, 0x00, 48, 48 );
+  TEST_VVCFG( 264, 32, 10, 0x00, 49, 48 );
+  TEST_VVCFG( 265, 32, 10, 0x00, 47, 47 );
+
+  TEST_VVCFG( 266, 32, 11, 0xf8, 18, 18 );
+  TEST_VVCFG( 267, 32, 11, 0xf8, 19, 18 );
+  TEST_VVCFG( 268, 32, 11, 0xf8, 17, 17 );
+
+  TEST_VVCFG( 269, 32, 11, 0x00, 48, 48 );
+  TEST_VVCFG( 270, 32, 11, 0x00, 49, 48 );
+  TEST_VVCFG( 271, 32, 11, 0x00, 47, 47 );
+
+  TEST_VVCFG( 272, 32, 12, 0xf8, 15, 15 );
+  TEST_VVCFG( 273, 32, 12, 0xf8, 16, 15 );
+  TEST_VVCFG( 274, 32, 12, 0xf8, 14, 14 );
+
+  TEST_VVCFG( 275, 32, 12, 0x00, 40, 40 );
+  TEST_VVCFG( 276, 32, 12, 0x00, 41, 40 );
+  TEST_VVCFG( 277, 32, 12, 0x00, 39, 39 );
+
+  TEST_VVCFG( 278, 32, 13, 0xf8, 15, 15 );
+  TEST_VVCFG( 279, 32, 13, 0xf8, 16, 15 );
+  TEST_VVCFG( 280, 32, 13, 0xf8, 14, 14 );
+
+  TEST_VVCFG( 281, 32, 13, 0x00, 40, 40 );
+  TEST_VVCFG( 282, 32, 13, 0x00, 41, 40 );
+  TEST_VVCFG( 283, 32, 13, 0x00, 39, 39 );
+
+  TEST_VVCFG( 284, 32, 14, 0xf8, 15, 15 );
+  TEST_VVCFG( 285, 32, 14, 0xf8, 16, 15 );
+  TEST_VVCFG( 286, 32, 14, 0xf8, 14, 14 );
+
+  TEST_VVCFG( 287, 32, 14, 0x00, 40, 40 );
+  TEST_VVCFG( 288, 32, 14, 0x00, 41, 40 );
+  TEST_VVCFG( 289, 32, 14, 0x00, 39, 39 );
+
+  TEST_VVCFG( 290, 32, 15, 0xf8, 15, 15 );
+  TEST_VVCFG( 291, 32, 15, 0xf8, 16, 15 );
+  TEST_VVCFG( 292, 32, 15, 0xf8, 14, 14 );
+
+  TEST_VVCFG( 293, 32, 15, 0x00, 40, 40 );
+  TEST_VVCFG( 294, 32, 15, 0x00, 41, 40 );
+  TEST_VVCFG( 295, 32, 15, 0x00, 39, 39 );
+
+  TEST_VVCFG( 296, 32, 16, 0xf8, 15, 15 );
+  TEST_VVCFG( 297, 32, 16, 0xf8, 16, 15 );
+  TEST_VVCFG( 298, 32, 16, 0xf8, 14, 14 );
+
+  TEST_VVCFG( 299, 32, 16, 0x00, 40, 40 );
+  TEST_VVCFG( 300, 32, 16, 0x00, 41, 40 );
+  TEST_VVCFG( 301, 32, 16, 0x00, 39, 39 );
+
+  TEST_VVCFG( 302, 32, 17, 0xf8, 15, 15 );
+  TEST_VVCFG( 303, 32, 17, 0xf8, 16, 15 );
+  TEST_VVCFG( 304, 32, 17, 0xf8, 14, 14 );
+
+  TEST_VVCFG( 305, 32, 17, 0x00, 40, 40 );
+  TEST_VVCFG( 306, 32, 17, 0x00, 41, 40 );
+  TEST_VVCFG( 307, 32, 17, 0x00, 39, 39 );
+
+  TEST_VVCFG( 308, 32, 18, 0xf8, 15, 15 );
+  TEST_VVCFG( 309, 32, 18, 0xf8, 16, 15 );
+  TEST_VVCFG( 310, 32, 18, 0xf8, 14, 14 );
+
+  TEST_VVCFG( 311, 32, 18, 0x00, 40, 40 );
+  TEST_VVCFG( 312, 32, 18, 0x00, 41, 40 );
+  TEST_VVCFG( 313, 32, 18, 0x00, 39, 39 );
+
+  TEST_VVCFG( 314, 32, 19, 0xf8, 15, 15 );
+  TEST_VVCFG( 315, 32, 19, 0xf8, 16, 15 );
+  TEST_VVCFG( 316, 32, 19, 0xf8, 14, 14 );
+
+  TEST_VVCFG( 317, 32, 19, 0x00, 40, 40 );
+  TEST_VVCFG( 318, 32, 19, 0x00, 41, 40 );
+  TEST_VVCFG( 319, 32, 19, 0x00, 39, 39 );
+
+  TEST_VVCFG( 320, 32, 20, 0xf8, 15, 15 );
+  TEST_VVCFG( 321, 32, 20, 0xf8, 16, 15 );
+  TEST_VVCFG( 322, 32, 20, 0xf8, 14, 14 );
+
+  TEST_VVCFG( 323, 32, 20, 0x00, 40, 40 );
+  TEST_VVCFG( 324, 32, 20, 0x00, 41, 40 );
+  TEST_VVCFG( 325, 32, 20, 0x00, 39, 39 );
+
+  TEST_VVCFG( 326, 32, 21, 0xf8, 12, 12 );
+  TEST_VVCFG( 327, 32, 21, 0xf8, 13, 12 );
+  TEST_VVCFG( 328, 32, 21, 0xf8, 11, 11 );
+
+  TEST_VVCFG( 329, 32, 21, 0x00, 32, 32 );
+  TEST_VVCFG( 330, 32, 21, 0x00, 33, 32 );
+  TEST_VVCFG( 331, 32, 21, 0x00, 31, 31 );
+
+  TEST_VVCFG( 332, 32, 22, 0xf8, 12, 12 );
+  TEST_VVCFG( 333, 32, 22, 0xf8, 13, 12 );
+  TEST_VVCFG( 334, 32, 22, 0xf8, 11, 11 );
+
+  TEST_VVCFG( 335, 32, 22, 0x00, 32, 32 );
+  TEST_VVCFG( 336, 32, 22, 0x00, 33, 32 );
+  TEST_VVCFG( 337, 32, 22, 0x00, 31, 31 );
+
+  TEST_VVCFG( 338, 32, 23, 0xf8, 12, 12 );
+  TEST_VVCFG( 339, 32, 23, 0xf8, 13, 12 );
+  TEST_VVCFG( 340, 32, 23, 0xf8, 11, 11 );
+
+  TEST_VVCFG( 341, 32, 23, 0x00, 32, 32 );
+  TEST_VVCFG( 342, 32, 23, 0x00, 33, 32 );
+  TEST_VVCFG( 343, 32, 23, 0x00, 31, 31 );
+
+  TEST_VVCFG( 344, 32, 24, 0xf8, 12, 12 );
+  TEST_VVCFG( 345, 32, 24, 0xf8, 13, 12 );
+  TEST_VVCFG( 346, 32, 24, 0xf8, 11, 11 );
+
+  TEST_VVCFG( 347, 32, 24, 0x00, 32, 32 );
+  TEST_VVCFG( 348, 32, 24, 0x00, 33, 32 );
+  TEST_VVCFG( 349, 32, 24, 0x00, 31, 31 );
+
+  TEST_VVCFG( 350, 32, 25, 0xf8, 12, 12 );
+  TEST_VVCFG( 351, 32, 25, 0xf8, 13, 12 );
+  TEST_VVCFG( 352, 32, 25, 0xf8, 11, 11 );
+
+  TEST_VVCFG( 353, 32, 25, 0x00, 32, 32 );
+  TEST_VVCFG( 354, 32, 25, 0x00, 33, 32 );
+  TEST_VVCFG( 355, 32, 25, 0x00, 31, 31 );
+
+  TEST_VVCFG( 356, 32, 26, 0xf8, 12, 12 );
+  TEST_VVCFG( 357, 32, 26, 0xf8, 13, 12 );
+  TEST_VVCFG( 358, 32, 26, 0xf8, 11, 11 );
+
+  TEST_VVCFG( 359, 32, 26, 0x00, 32, 32 );
+  TEST_VVCFG( 360, 32, 26, 0x00, 33, 32 );
+  TEST_VVCFG( 361, 32, 26, 0x00, 31, 31 );
+
+  TEST_VVCFG( 362, 32, 27, 0xf8, 12, 12 );
+  TEST_VVCFG( 363, 32, 27, 0xf8, 13, 12 );
+  TEST_VVCFG( 364, 32, 27, 0xf8, 11, 11 );
+
+  TEST_VVCFG( 365, 32, 27, 0x00, 32, 32 );
+  TEST_VVCFG( 366, 32, 27, 0x00, 33, 32 );
+  TEST_VVCFG( 367, 32, 27, 0x00, 31, 31 );
+
+  TEST_VVCFG( 368, 32, 28, 0xf8, 12, 12 );
+  TEST_VVCFG( 369, 32, 28, 0xf8, 13, 12 );
+  TEST_VVCFG( 370, 32, 28, 0xf8, 11, 11 );
+
+  TEST_VVCFG( 371, 32, 28, 0x00, 32, 32 );
+  TEST_VVCFG( 372, 32, 28, 0x00, 33, 32 );
+  TEST_VVCFG( 373, 32, 28, 0x00, 31, 31 );
+
+  TEST_VVCFG( 374, 32, 29, 0xf8, 12, 12 );
+  TEST_VVCFG( 375, 32, 29, 0xf8, 13, 12 );
+  TEST_VVCFG( 376, 32, 29, 0xf8, 11, 11 );
+
+  TEST_VVCFG( 377, 32, 29, 0x00, 32, 32 );
+  TEST_VVCFG( 378, 32, 29, 0x00, 33, 32 );
+  TEST_VVCFG( 379, 32, 29, 0x00, 31, 31 );
+
+  TEST_VVCFG( 380, 32, 30, 0xf8, 12, 12 );
+  TEST_VVCFG( 381, 32, 30, 0xf8, 13, 12 );
+  TEST_VVCFG( 382, 32, 30, 0xf8, 11, 11 );
+
+  TEST_VVCFG( 383, 32, 30, 0x00, 32, 32 );
+  TEST_VVCFG( 384, 32, 30, 0x00, 33, 32 );
+  TEST_VVCFG( 385, 32, 30, 0x00, 31, 31 );
+
+  TEST_VVCFG( 386, 32, 31, 0xf8, 12, 12 );
+  TEST_VVCFG( 387, 32, 31, 0xf8, 13, 12 );
+  TEST_VVCFG( 388, 32, 31, 0xf8, 11, 11 );
+
+  TEST_VVCFG( 389, 32, 31, 0x00, 32, 32 );
+  TEST_VVCFG( 390, 32, 31, 0x00, 33, 32 );
+  TEST_VVCFG( 391, 32, 31, 0x00, 31, 31 );
+
+  TEST_VVCFG( 392, 32, 32, 0xf8, 12, 12 );
+  TEST_VVCFG( 393, 32, 32, 0xf8, 13, 12 );
+  TEST_VVCFG( 394, 32, 32, 0xf8, 11, 11 );
+
+  TEST_VVCFG( 395, 32, 32, 0x00, 32, 32 );
+  TEST_VVCFG( 396, 32, 32, 0x00, 33, 32 );
+  TEST_VVCFG( 397, 32, 32, 0x00, 31, 31 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END

diff --git a/isa/rv64uv/vsetcfgi.S b/isa/rv64uv/vsetcfgi.S
new file mode 100644 (file)
index 0000000..4a23185
--- /dev/null
+++ b/isa/rv64uv/vsetcfgi.S
@@ -0,0 +1,559 @@
+#*****************************************************************************
+# vsetcfgi.S
+#-----------------------------------------------------------------------------
+#
+# Test vsetcfg instruction with immediates.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_VSETCFGIVL( 2, 0, 0, 0xf8, 768, 768 );
+  TEST_VSETCFGIVL( 3, 0, 0, 0xf8, 769, 768 );
+  TEST_VSETCFGIVL( 4, 0, 0, 0xf8, 767, 767 );
+
+  TEST_VSETCFGIVL( 5, 0, 0, 0x00, 2048, 2048 );
+  TEST_VSETCFGIVL( 6, 0, 0, 0x00, 2049, 2048 );
+  TEST_VSETCFGIVL( 7, 0, 0, 0x00, 2047, 2047 );
+
+  TEST_VSETCFGIVL( 8, 1, 0, 0xf8, 768, 768 );
+  TEST_VSETCFGIVL( 9, 1, 0, 0xf8, 769, 768 );
+  TEST_VSETCFGIVL( 10, 1, 0, 0xf8, 767, 767 );
+
+  TEST_VSETCFGIVL( 11, 1, 0, 0x00, 2048, 2048 );
+  TEST_VSETCFGIVL( 12, 1, 0, 0x00, 2049, 2048 );
+  TEST_VSETCFGIVL( 13, 1, 0, 0x00, 2047, 2047 );
+
+  TEST_VSETCFGIVL( 14, 2, 0, 0xf8, 768, 768 );
+  TEST_VSETCFGIVL( 15, 2, 0, 0xf8, 769, 768 );
+  TEST_VSETCFGIVL( 16, 2, 0, 0xf8, 767, 767 );
+
+  TEST_VSETCFGIVL( 17, 2, 0, 0x00, 2048, 2048 );
+  TEST_VSETCFGIVL( 18, 2, 0, 0x00, 2049, 2048 );
+  TEST_VSETCFGIVL( 19, 2, 0, 0x00, 2047, 2047 );
+
+  TEST_VSETCFGIVL( 20, 3, 0, 0xf8, 384, 384 );
+  TEST_VSETCFGIVL( 21, 3, 0, 0xf8, 385, 384 );
+  TEST_VSETCFGIVL( 22, 3, 0, 0xf8, 383, 383 );
+
+  TEST_VSETCFGIVL( 23, 3, 0, 0x00, 1024, 1024 );
+  TEST_VSETCFGIVL( 24, 3, 0, 0x00, 1025, 1024 );
+  TEST_VSETCFGIVL( 25, 3, 0, 0x00, 1023, 1023 );
+
+  TEST_VSETCFGIVL( 26, 4, 0, 0xf8, 255, 255 );
+  TEST_VSETCFGIVL( 27, 4, 0, 0xf8, 256, 255 );
+  TEST_VSETCFGIVL( 28, 4, 0, 0xf8, 254, 254 );
+
+  TEST_VSETCFGIVL( 29, 4, 0, 0x00, 680, 680 );
+  TEST_VSETCFGIVL( 30, 4, 0, 0x00, 681, 680 );
+  TEST_VSETCFGIVL( 31, 4, 0, 0x00, 679, 679 );
+
+  TEST_VSETCFGIVL( 32, 5, 0, 0xf8, 192, 192 );
+  TEST_VSETCFGIVL( 33, 5, 0, 0xf8, 193, 192 );
+  TEST_VSETCFGIVL( 34, 5, 0, 0xf8, 191, 191 );
+
+  TEST_VSETCFGIVL( 35, 5, 0, 0x00, 512, 512 );
+  TEST_VSETCFGIVL( 36, 5, 0, 0x00, 513, 512 );
+  TEST_VSETCFGIVL( 37, 5, 0, 0x00, 511, 511 );
+
+  TEST_VSETCFGIVL( 38, 6, 0, 0xf8, 153, 153 );
+  TEST_VSETCFGIVL( 39, 6, 0, 0xf8, 154, 153 );
+  TEST_VSETCFGIVL( 40, 6, 0, 0xf8, 152, 152 );
+
+  TEST_VSETCFGIVL( 41, 6, 0, 0x00, 408, 408 );
+  TEST_VSETCFGIVL( 42, 6, 0, 0x00, 409, 408 );
+  TEST_VSETCFGIVL( 43, 6, 0, 0x00, 407, 407 );
+
+  TEST_VSETCFGIVL( 44, 7, 0, 0xf8, 126, 126 );
+  TEST_VSETCFGIVL( 45, 7, 0, 0xf8, 127, 126 );
+  TEST_VSETCFGIVL( 46, 7, 0, 0xf8, 125, 125 );
+
+  TEST_VSETCFGIVL( 47, 7, 0, 0x00, 336, 336 );
+  TEST_VSETCFGIVL( 48, 7, 0, 0x00, 337, 336 );
+  TEST_VSETCFGIVL( 49, 7, 0, 0x00, 335, 335 );
+
+  TEST_VSETCFGIVL( 50, 8, 0, 0xf8, 108, 108 );
+  TEST_VSETCFGIVL( 51, 8, 0, 0xf8, 109, 108 );
+  TEST_VSETCFGIVL( 52, 8, 0, 0xf8, 107, 107 );
+
+  TEST_VSETCFGIVL( 53, 8, 0, 0x00, 288, 288 );
+  TEST_VSETCFGIVL( 54, 8, 0, 0x00, 289, 288 );
+  TEST_VSETCFGIVL( 55, 8, 0, 0x00, 287, 287 );
+
+  TEST_VSETCFGIVL( 56, 9, 0, 0xf8, 96, 96 );
+  TEST_VSETCFGIVL( 57, 9, 0, 0xf8, 97, 96 );
+  TEST_VSETCFGIVL( 58, 9, 0, 0xf8, 95, 95 );
+
+  TEST_VSETCFGIVL( 59, 9, 0, 0x00, 256, 256 );
+  TEST_VSETCFGIVL( 60, 9, 0, 0x00, 257, 256 );
+  TEST_VSETCFGIVL( 61, 9, 0, 0x00, 255, 255 );
+
+  TEST_VSETCFGIVL( 62, 10, 0, 0xf8, 84, 84 );
+  TEST_VSETCFGIVL( 63, 10, 0, 0xf8, 85, 84 );
+  TEST_VSETCFGIVL( 64, 10, 0, 0xf8, 83, 83 );
+
+  TEST_VSETCFGIVL( 65, 10, 0, 0x00, 224, 224 );
+  TEST_VSETCFGIVL( 66, 10, 0, 0x00, 225, 224 );
+  TEST_VSETCFGIVL( 67, 10, 0, 0x00, 223, 223 );
+
+  TEST_VSETCFGIVL( 68, 11, 0, 0xf8, 75, 75 );
+  TEST_VSETCFGIVL( 69, 11, 0, 0xf8, 76, 75 );
+  TEST_VSETCFGIVL( 70, 11, 0, 0xf8, 74, 74 );
+
+  TEST_VSETCFGIVL( 71, 11, 0, 0x00, 200, 200 );
+  TEST_VSETCFGIVL( 72, 11, 0, 0x00, 201, 200 );
+  TEST_VSETCFGIVL( 73, 11, 0, 0x00, 199, 199 );
+
+  TEST_VSETCFGIVL( 74, 12, 0, 0xf8, 69, 69 );
+  TEST_VSETCFGIVL( 75, 12, 0, 0xf8, 70, 69 );
+  TEST_VSETCFGIVL( 76, 12, 0, 0xf8, 68, 68 );
+
+  TEST_VSETCFGIVL( 77, 12, 0, 0x00, 184, 184 );
+  TEST_VSETCFGIVL( 78, 12, 0, 0x00, 185, 184 );
+  TEST_VSETCFGIVL( 79, 12, 0, 0x00, 183, 183 );
+
+  TEST_VSETCFGIVL( 80, 13, 0, 0xf8, 63, 63 );
+  TEST_VSETCFGIVL( 81, 13, 0, 0xf8, 64, 63 );
+  TEST_VSETCFGIVL( 82, 13, 0, 0xf8, 62, 62 );
+
+  TEST_VSETCFGIVL( 83, 13, 0, 0x00, 168, 168 );
+  TEST_VSETCFGIVL( 84, 13, 0, 0x00, 169, 168 );
+  TEST_VSETCFGIVL( 85, 13, 0, 0x00, 167, 167 );
+
+  TEST_VSETCFGIVL( 86, 14, 0, 0xf8, 57, 57 );
+  TEST_VSETCFGIVL( 87, 14, 0, 0xf8, 58, 57 );
+  TEST_VSETCFGIVL( 88, 14, 0, 0xf8, 56, 56 );
+
+  TEST_VSETCFGIVL( 89, 14, 0, 0x00, 152, 152 );
+  TEST_VSETCFGIVL( 90, 14, 0, 0x00, 153, 152 );
+  TEST_VSETCFGIVL( 91, 14, 0, 0x00, 151, 151 );
+
+  TEST_VSETCFGIVL( 92, 15, 0, 0xf8, 54, 54 );
+  TEST_VSETCFGIVL( 93, 15, 0, 0xf8, 55, 54 );
+  TEST_VSETCFGIVL( 94, 15, 0, 0xf8, 53, 53 );
+
+  TEST_VSETCFGIVL( 95, 15, 0, 0x00, 144, 144 );
+  TEST_VSETCFGIVL( 96, 15, 0, 0x00, 145, 144 );
+  TEST_VSETCFGIVL( 97, 15, 0, 0x00, 143, 143 );
+
+  TEST_VSETCFGIVL( 98, 16, 0, 0xf8, 51, 51 );
+  TEST_VSETCFGIVL( 99, 16, 0, 0xf8, 52, 51 );
+  TEST_VSETCFGIVL( 100, 16, 0, 0xf8, 50, 50 );
+
+  TEST_VSETCFGIVL( 101, 16, 0, 0x00, 136, 136 );
+  TEST_VSETCFGIVL( 102, 16, 0, 0x00, 137, 136 );
+  TEST_VSETCFGIVL( 103, 16, 0, 0x00, 135, 135 );
+
+  TEST_VSETCFGIVL( 104, 17, 0, 0xf8, 48, 48 );
+  TEST_VSETCFGIVL( 105, 17, 0, 0xf8, 49, 48 );
+  TEST_VSETCFGIVL( 106, 17, 0, 0xf8, 47, 47 );
+
+  TEST_VSETCFGIVL( 107, 17, 0, 0x00, 128, 128 );
+  TEST_VSETCFGIVL( 108, 17, 0, 0x00, 129, 128 );
+  TEST_VSETCFGIVL( 109, 17, 0, 0x00, 127, 127 );
+
+  TEST_VSETCFGIVL( 110, 18, 0, 0xf8, 45, 45 );
+  TEST_VSETCFGIVL( 111, 18, 0, 0xf8, 46, 45 );
+  TEST_VSETCFGIVL( 112, 18, 0, 0xf8, 44, 44 );
+
+  TEST_VSETCFGIVL( 113, 18, 0, 0x00, 120, 120 );
+  TEST_VSETCFGIVL( 114, 18, 0, 0x00, 121, 120 );
+  TEST_VSETCFGIVL( 115, 18, 0, 0x00, 119, 119 );
+
+  TEST_VSETCFGIVL( 116, 19, 0, 0xf8, 42, 42 );
+  TEST_VSETCFGIVL( 117, 19, 0, 0xf8, 43, 42 );
+  TEST_VSETCFGIVL( 118, 19, 0, 0xf8, 41, 41 );
+
+  TEST_VSETCFGIVL( 119, 19, 0, 0x00, 112, 112 );
+  TEST_VSETCFGIVL( 120, 19, 0, 0x00, 113, 112 );
+  TEST_VSETCFGIVL( 121, 19, 0, 0x00, 111, 111 );
+
+  TEST_VSETCFGIVL( 122, 20, 0, 0xf8, 39, 39 );
+  TEST_VSETCFGIVL( 123, 20, 0, 0xf8, 40, 39 );
+  TEST_VSETCFGIVL( 124, 20, 0, 0xf8, 38, 38 );
+
+  TEST_VSETCFGIVL( 125, 20, 0, 0x00, 104, 104 );
+  TEST_VSETCFGIVL( 126, 20, 0, 0x00, 105, 104 );
+  TEST_VSETCFGIVL( 127, 20, 0, 0x00, 103, 103 );
+
+  TEST_VSETCFGIVL( 128, 21, 0, 0xf8, 36, 36 );
+  TEST_VSETCFGIVL( 129, 21, 0, 0xf8, 37, 36 );
+  TEST_VSETCFGIVL( 130, 21, 0, 0xf8, 35, 35 );
+
+  TEST_VSETCFGIVL( 131, 21, 0, 0x00, 96, 96 );
+  TEST_VSETCFGIVL( 132, 21, 0, 0x00, 97, 96 );
+  TEST_VSETCFGIVL( 133, 21, 0, 0x00, 95, 95 );
+
+  TEST_VSETCFGIVL( 134, 22, 0, 0xf8, 36, 36 );
+  TEST_VSETCFGIVL( 135, 22, 0, 0xf8, 37, 36 );
+  TEST_VSETCFGIVL( 136, 22, 0, 0xf8, 35, 35 );
+
+  TEST_VSETCFGIVL( 137, 22, 0, 0x00, 96, 96 );
+  TEST_VSETCFGIVL( 138, 22, 0, 0x00, 97, 96 );
+  TEST_VSETCFGIVL( 139, 22, 0, 0x00, 95, 95 );
+
+  TEST_VSETCFGIVL( 140, 23, 0, 0xf8, 33, 33 );
+  TEST_VSETCFGIVL( 141, 23, 0, 0xf8, 34, 33 );
+  TEST_VSETCFGIVL( 142, 23, 0, 0xf8, 32, 32 );
+
+  TEST_VSETCFGIVL( 143, 23, 0, 0x00, 88, 88 );
+  TEST_VSETCFGIVL( 144, 23, 0, 0x00, 89, 88 );
+  TEST_VSETCFGIVL( 145, 23, 0, 0x00, 87, 87 );
+
+  TEST_VSETCFGIVL( 146, 24, 0, 0xf8, 33, 33 );
+  TEST_VSETCFGIVL( 147, 24, 0, 0xf8, 34, 33 );
+  TEST_VSETCFGIVL( 148, 24, 0, 0xf8, 32, 32 );
+
+  TEST_VSETCFGIVL( 149, 24, 0, 0x00, 88, 88 );
+  TEST_VSETCFGIVL( 150, 24, 0, 0x00, 89, 88 );
+  TEST_VSETCFGIVL( 151, 24, 0, 0x00, 87, 87 );
+
+  TEST_VSETCFGIVL( 152, 25, 0, 0xf8, 30, 30 );
+  TEST_VSETCFGIVL( 153, 25, 0, 0xf8, 31, 30 );
+  TEST_VSETCFGIVL( 154, 25, 0, 0xf8, 29, 29 );
+
+  TEST_VSETCFGIVL( 155, 25, 0, 0x00, 80, 80 );
+  TEST_VSETCFGIVL( 156, 25, 0, 0x00, 81, 80 );
+  TEST_VSETCFGIVL( 157, 25, 0, 0x00, 79, 79 );
+
+  TEST_VSETCFGIVL( 158, 26, 0, 0xf8, 30, 30 );
+  TEST_VSETCFGIVL( 159, 26, 0, 0xf8, 31, 30 );
+  TEST_VSETCFGIVL( 160, 26, 0, 0xf8, 29, 29 );
+
+  TEST_VSETCFGIVL( 161, 26, 0, 0x00, 80, 80 );
+  TEST_VSETCFGIVL( 162, 26, 0, 0x00, 81, 80 );
+  TEST_VSETCFGIVL( 163, 26, 0, 0x00, 79, 79 );
+
+  TEST_VSETCFGIVL( 164, 27, 0, 0xf8, 27, 27 );
+  TEST_VSETCFGIVL( 165, 27, 0, 0xf8, 28, 27 );
+  TEST_VSETCFGIVL( 166, 27, 0, 0xf8, 26, 26 );
+
+  TEST_VSETCFGIVL( 167, 27, 0, 0x00, 72, 72 );
+  TEST_VSETCFGIVL( 168, 27, 0, 0x00, 73, 72 );
+  TEST_VSETCFGIVL( 169, 27, 0, 0x00, 71, 71 );
+
+  TEST_VSETCFGIVL( 170, 28, 0, 0xf8, 27, 27 );
+  TEST_VSETCFGIVL( 171, 28, 0, 0xf8, 28, 27 );
+  TEST_VSETCFGIVL( 172, 28, 0, 0xf8, 26, 26 );
+
+  TEST_VSETCFGIVL( 173, 28, 0, 0x00, 72, 72 );
+  TEST_VSETCFGIVL( 174, 28, 0, 0x00, 73, 72 );
+  TEST_VSETCFGIVL( 175, 28, 0, 0x00, 71, 71 );
+
+  TEST_VSETCFGIVL( 176, 29, 0, 0xf8, 27, 27 );
+  TEST_VSETCFGIVL( 177, 29, 0, 0xf8, 28, 27 );
+  TEST_VSETCFGIVL( 178, 29, 0, 0xf8, 26, 26 );
+
+  TEST_VSETCFGIVL( 179, 29, 0, 0x00, 72, 72 );
+  TEST_VSETCFGIVL( 180, 29, 0, 0x00, 73, 72 );
+  TEST_VSETCFGIVL( 181, 29, 0, 0x00, 71, 71 );
+
+  TEST_VSETCFGIVL( 182, 30, 0, 0xf8, 24, 24 );
+  TEST_VSETCFGIVL( 183, 30, 0, 0xf8, 25, 24 );
+  TEST_VSETCFGIVL( 184, 30, 0, 0xf8, 23, 23 );
+
+  TEST_VSETCFGIVL( 185, 30, 0, 0x00, 64, 64 );
+  TEST_VSETCFGIVL( 186, 30, 0, 0x00, 65, 64 );
+  TEST_VSETCFGIVL( 187, 30, 0, 0x00, 63, 63 );
+
+  TEST_VSETCFGIVL( 188, 31, 0, 0xf8, 24, 24 );
+  TEST_VSETCFGIVL( 189, 31, 0, 0xf8, 25, 24 );
+  TEST_VSETCFGIVL( 190, 31, 0, 0xf8, 23, 23 );
+
+  TEST_VSETCFGIVL( 191, 31, 0, 0x00, 64, 64 );
+  TEST_VSETCFGIVL( 192, 31, 0, 0x00, 65, 64 );
+  TEST_VSETCFGIVL( 193, 31, 0, 0x00, 63, 63 );
+
+  TEST_VSETCFGIVL( 194, 32, 0, 0xf8, 24, 24 );
+  TEST_VSETCFGIVL( 195, 32, 0, 0xf8, 25, 24 );
+  TEST_VSETCFGIVL( 196, 32, 0, 0xf8, 23, 23 );
+
+  TEST_VSETCFGIVL( 197, 32, 0, 0x00, 64, 64 );
+  TEST_VSETCFGIVL( 198, 32, 0, 0x00, 65, 64 );
+  TEST_VSETCFGIVL( 199, 32, 0, 0x00, 63, 63 );
+
+  TEST_VSETCFGIVL( 200, 32, 0, 0xf8, 24, 24 );
+  TEST_VSETCFGIVL( 201, 32, 0, 0xf8, 25, 24 );
+  TEST_VSETCFGIVL( 202, 32, 0, 0xf8, 23, 23 );
+
+  TEST_VSETCFGIVL( 203, 32, 0, 0x00, 64, 64 );
+  TEST_VSETCFGIVL( 204, 32, 0, 0x00, 65, 64 );
+  TEST_VSETCFGIVL( 205, 32, 0, 0x00, 63, 63 );
+
+  TEST_VSETCFGIVL( 206, 32, 1, 0xf8, 24, 24 );
+  TEST_VSETCFGIVL( 207, 32, 1, 0xf8, 25, 24 );
+  TEST_VSETCFGIVL( 208, 32, 1, 0xf8, 23, 23 );
+
+  TEST_VSETCFGIVL( 209, 32, 1, 0x00, 64, 64 );
+  TEST_VSETCFGIVL( 210, 32, 1, 0x00, 65, 64 );
+  TEST_VSETCFGIVL( 211, 32, 1, 0x00, 63, 63 );
+
+  TEST_VSETCFGIVL( 212, 32, 2, 0xf8, 21, 21 );
+  TEST_VSETCFGIVL( 213, 32, 2, 0xf8, 22, 21 );
+  TEST_VSETCFGIVL( 214, 32, 2, 0xf8, 20, 20 );
+
+  TEST_VSETCFGIVL( 215, 32, 2, 0x00, 56, 56 );
+  TEST_VSETCFGIVL( 216, 32, 2, 0x00, 57, 56 );
+  TEST_VSETCFGIVL( 217, 32, 2, 0x00, 55, 55 );
+
+  TEST_VSETCFGIVL( 218, 32, 3, 0xf8, 21, 21 );
+  TEST_VSETCFGIVL( 219, 32, 3, 0xf8, 22, 21 );
+  TEST_VSETCFGIVL( 220, 32, 3, 0xf8, 20, 20 );
+
+  TEST_VSETCFGIVL( 221, 32, 3, 0x00, 56, 56 );
+  TEST_VSETCFGIVL( 222, 32, 3, 0x00, 57, 56 );
+  TEST_VSETCFGIVL( 223, 32, 3, 0x00, 55, 55 );
+
+  TEST_VSETCFGIVL( 224, 32, 4, 0xf8, 21, 21 );
+  TEST_VSETCFGIVL( 225, 32, 4, 0xf8, 22, 21 );
+  TEST_VSETCFGIVL( 226, 32, 4, 0xf8, 20, 20 );
+
+  TEST_VSETCFGIVL( 227, 32, 4, 0x00, 56, 56 );
+  TEST_VSETCFGIVL( 228, 32, 4, 0x00, 57, 56 );
+  TEST_VSETCFGIVL( 229, 32, 4, 0x00, 55, 55 );
+
+  TEST_VSETCFGIVL( 230, 32, 5, 0xf8, 21, 21 );
+  TEST_VSETCFGIVL( 231, 32, 5, 0xf8, 22, 21 );
+  TEST_VSETCFGIVL( 232, 32, 5, 0xf8, 20, 20 );
+
+  TEST_VSETCFGIVL( 233, 32, 5, 0x00, 56, 56 );
+  TEST_VSETCFGIVL( 234, 32, 5, 0x00, 57, 56 );
+  TEST_VSETCFGIVL( 235, 32, 5, 0x00, 55, 55 );
+
+  TEST_VSETCFGIVL( 236, 32, 6, 0xf8, 18, 18 );
+  TEST_VSETCFGIVL( 237, 32, 6, 0xf8, 19, 18 );
+  TEST_VSETCFGIVL( 238, 32, 6, 0xf8, 17, 17 );
+
+  TEST_VSETCFGIVL( 239, 32, 6, 0x00, 48, 48 );
+  TEST_VSETCFGIVL( 240, 32, 6, 0x00, 49, 48 );
+  TEST_VSETCFGIVL( 241, 32, 6, 0x00, 47, 47 );
+
+  TEST_VSETCFGIVL( 242, 32, 7, 0xf8, 18, 18 );
+  TEST_VSETCFGIVL( 243, 32, 7, 0xf8, 19, 18 );
+  TEST_VSETCFGIVL( 244, 32, 7, 0xf8, 17, 17 );
+
+  TEST_VSETCFGIVL( 245, 32, 7, 0x00, 48, 48 );
+  TEST_VSETCFGIVL( 246, 32, 7, 0x00, 49, 48 );
+  TEST_VSETCFGIVL( 247, 32, 7, 0x00, 47, 47 );
+
+  TEST_VSETCFGIVL( 248, 32, 8, 0xf8, 18, 18 );
+  TEST_VSETCFGIVL( 249, 32, 8, 0xf8, 19, 18 );
+  TEST_VSETCFGIVL( 250, 32, 8, 0xf8, 17, 17 );
+
+  TEST_VSETCFGIVL( 251, 32, 8, 0x00, 48, 48 );
+  TEST_VSETCFGIVL( 252, 32, 8, 0x00, 49, 48 );
+  TEST_VSETCFGIVL( 253, 32, 8, 0x00, 47, 47 );
+
+  TEST_VSETCFGIVL( 254, 32, 9, 0xf8, 18, 18 );
+  TEST_VSETCFGIVL( 255, 32, 9, 0xf8, 19, 18 );
+  TEST_VSETCFGIVL( 256, 32, 9, 0xf8, 17, 17 );
+
+  TEST_VSETCFGIVL( 257, 32, 9, 0x00, 48, 48 );
+  TEST_VSETCFGIVL( 258, 32, 9, 0x00, 49, 48 );
+  TEST_VSETCFGIVL( 259, 32, 9, 0x00, 47, 47 );
+
+  TEST_VSETCFGIVL( 260, 32, 10, 0xf8, 18, 18 );
+  TEST_VSETCFGIVL( 261, 32, 10, 0xf8, 19, 18 );
+  TEST_VSETCFGIVL( 262, 32, 10, 0xf8, 17, 17 );
+
+  TEST_VSETCFGIVL( 263, 32, 10, 0x00, 48, 48 );
+  TEST_VSETCFGIVL( 264, 32, 10, 0x00, 49, 48 );
+  TEST_VSETCFGIVL( 265, 32, 10, 0x00, 47, 47 );
+
+  TEST_VSETCFGIVL( 266, 32, 11, 0xf8, 18, 18 );
+  TEST_VSETCFGIVL( 267, 32, 11, 0xf8, 19, 18 );
+  TEST_VSETCFGIVL( 268, 32, 11, 0xf8, 17, 17 );
+
+  TEST_VSETCFGIVL( 269, 32, 11, 0x00, 48, 48 );
+  TEST_VSETCFGIVL( 270, 32, 11, 0x00, 49, 48 );
+  TEST_VSETCFGIVL( 271, 32, 11, 0x00, 47, 47 );
+
+  TEST_VSETCFGIVL( 272, 32, 12, 0xf8, 15, 15 );
+  TEST_VSETCFGIVL( 273, 32, 12, 0xf8, 16, 15 );
+  TEST_VSETCFGIVL( 274, 32, 12, 0xf8, 14, 14 );
+
+  TEST_VSETCFGIVL( 275, 32, 12, 0x00, 40, 40 );
+  TEST_VSETCFGIVL( 276, 32, 12, 0x00, 41, 40 );
+  TEST_VSETCFGIVL( 277, 32, 12, 0x00, 39, 39 );
+
+  TEST_VSETCFGIVL( 278, 32, 13, 0xf8, 15, 15 );
+  TEST_VSETCFGIVL( 279, 32, 13, 0xf8, 16, 15 );
+  TEST_VSETCFGIVL( 280, 32, 13, 0xf8, 14, 14 );
+
+  TEST_VSETCFGIVL( 281, 32, 13, 0x00, 40, 40 );
+  TEST_VSETCFGIVL( 282, 32, 13, 0x00, 41, 40 );
+  TEST_VSETCFGIVL( 283, 32, 13, 0x00, 39, 39 );
+
+  TEST_VSETCFGIVL( 284, 32, 14, 0xf8, 15, 15 );
+  TEST_VSETCFGIVL( 285, 32, 14, 0xf8, 16, 15 );
+  TEST_VSETCFGIVL( 286, 32, 14, 0xf8, 14, 14 );
+
+  TEST_VSETCFGIVL( 287, 32, 14, 0x00, 40, 40 );
+  TEST_VSETCFGIVL( 288, 32, 14, 0x00, 41, 40 );
+  TEST_VSETCFGIVL( 289, 32, 14, 0x00, 39, 39 );
+
+  TEST_VSETCFGIVL( 290, 32, 15, 0xf8, 15, 15 );
+  TEST_VSETCFGIVL( 291, 32, 15, 0xf8, 16, 15 );
+  TEST_VSETCFGIVL( 292, 32, 15, 0xf8, 14, 14 );
+
+  TEST_VSETCFGIVL( 293, 32, 15, 0x00, 40, 40 );
+  TEST_VSETCFGIVL( 294, 32, 15, 0x00, 41, 40 );
+  TEST_VSETCFGIVL( 295, 32, 15, 0x00, 39, 39 );
+
+  TEST_VSETCFGIVL( 296, 32, 16, 0xf8, 15, 15 );
+  TEST_VSETCFGIVL( 297, 32, 16, 0xf8, 16, 15 );
+  TEST_VSETCFGIVL( 298, 32, 16, 0xf8, 14, 14 );
+
+  TEST_VSETCFGIVL( 299, 32, 16, 0x00, 40, 40 );
+  TEST_VSETCFGIVL( 300, 32, 16, 0x00, 41, 40 );
+  TEST_VSETCFGIVL( 301, 32, 16, 0x00, 39, 39 );
+
+  TEST_VSETCFGIVL( 302, 32, 17, 0xf8, 15, 15 );
+  TEST_VSETCFGIVL( 303, 32, 17, 0xf8, 16, 15 );
+  TEST_VSETCFGIVL( 304, 32, 17, 0xf8, 14, 14 );
+
+  TEST_VSETCFGIVL( 305, 32, 17, 0x00, 40, 40 );
+  TEST_VSETCFGIVL( 306, 32, 17, 0x00, 41, 40 );
+  TEST_VSETCFGIVL( 307, 32, 17, 0x00, 39, 39 );
+
+  TEST_VSETCFGIVL( 308, 32, 18, 0xf8, 15, 15 );
+  TEST_VSETCFGIVL( 309, 32, 18, 0xf8, 16, 15 );
+  TEST_VSETCFGIVL( 310, 32, 18, 0xf8, 14, 14 );
+
+  TEST_VSETCFGIVL( 311, 32, 18, 0x00, 40, 40 );
+  TEST_VSETCFGIVL( 312, 32, 18, 0x00, 41, 40 );
+  TEST_VSETCFGIVL( 313, 32, 18, 0x00, 39, 39 );
+
+  TEST_VSETCFGIVL( 314, 32, 19, 0xf8, 15, 15 );
+  TEST_VSETCFGIVL( 315, 32, 19, 0xf8, 16, 15 );
+  TEST_VSETCFGIVL( 316, 32, 19, 0xf8, 14, 14 );
+
+  TEST_VSETCFGIVL( 317, 32, 19, 0x00, 40, 40 );
+  TEST_VSETCFGIVL( 318, 32, 19, 0x00, 41, 40 );
+  TEST_VSETCFGIVL( 319, 32, 19, 0x00, 39, 39 );
+
+  TEST_VSETCFGIVL( 320, 32, 20, 0xf8, 15, 15 );
+  TEST_VSETCFGIVL( 321, 32, 20, 0xf8, 16, 15 );
+  TEST_VSETCFGIVL( 322, 32, 20, 0xf8, 14, 14 );
+
+  TEST_VSETCFGIVL( 323, 32, 20, 0x00, 40, 40 );
+  TEST_VSETCFGIVL( 324, 32, 20, 0x00, 41, 40 );
+  TEST_VSETCFGIVL( 325, 32, 20, 0x00, 39, 39 );
+
+  TEST_VSETCFGIVL( 326, 32, 21, 0xf8, 12, 12 );
+  TEST_VSETCFGIVL( 327, 32, 21, 0xf8, 13, 12 );
+  TEST_VSETCFGIVL( 328, 32, 21, 0xf8, 11, 11 );
+
+  TEST_VSETCFGIVL( 329, 32, 21, 0x00, 32, 32 );
+  TEST_VSETCFGIVL( 330, 32, 21, 0x00, 33, 32 );
+  TEST_VSETCFGIVL( 331, 32, 21, 0x00, 31, 31 );
+
+  TEST_VSETCFGIVL( 332, 32, 22, 0xf8, 12, 12 );
+  TEST_VSETCFGIVL( 333, 32, 22, 0xf8, 13, 12 );
+  TEST_VSETCFGIVL( 334, 32, 22, 0xf8, 11, 11 );
+
+  TEST_VSETCFGIVL( 335, 32, 22, 0x00, 32, 32 );
+  TEST_VSETCFGIVL( 336, 32, 22, 0x00, 33, 32 );
+  TEST_VSETCFGIVL( 337, 32, 22, 0x00, 31, 31 );
+
+  TEST_VSETCFGIVL( 338, 32, 23, 0xf8, 12, 12 );
+  TEST_VSETCFGIVL( 339, 32, 23, 0xf8, 13, 12 );
+  TEST_VSETCFGIVL( 340, 32, 23, 0xf8, 11, 11 );
+
+  TEST_VSETCFGIVL( 341, 32, 23, 0x00, 32, 32 );
+  TEST_VSETCFGIVL( 342, 32, 23, 0x00, 33, 32 );
+  TEST_VSETCFGIVL( 343, 32, 23, 0x00, 31, 31 );
+
+  TEST_VSETCFGIVL( 344, 32, 24, 0xf8, 12, 12 );
+  TEST_VSETCFGIVL( 345, 32, 24, 0xf8, 13, 12 );
+  TEST_VSETCFGIVL( 346, 32, 24, 0xf8, 11, 11 );
+
+  TEST_VSETCFGIVL( 347, 32, 24, 0x00, 32, 32 );
+  TEST_VSETCFGIVL( 348, 32, 24, 0x00, 33, 32 );
+  TEST_VSETCFGIVL( 349, 32, 24, 0x00, 31, 31 );
+
+  TEST_VSETCFGIVL( 350, 32, 25, 0xf8, 12, 12 );
+  TEST_VSETCFGIVL( 351, 32, 25, 0xf8, 13, 12 );
+  TEST_VSETCFGIVL( 352, 32, 25, 0xf8, 11, 11 );
+
+  TEST_VSETCFGIVL( 353, 32, 25, 0x00, 32, 32 );
+  TEST_VSETCFGIVL( 354, 32, 25, 0x00, 33, 32 );
+  TEST_VSETCFGIVL( 355, 32, 25, 0x00, 31, 31 );
+
+  TEST_VSETCFGIVL( 356, 32, 26, 0xf8, 12, 12 );
+  TEST_VSETCFGIVL( 357, 32, 26, 0xf8, 13, 12 );
+  TEST_VSETCFGIVL( 358, 32, 26, 0xf8, 11, 11 );
+
+  TEST_VSETCFGIVL( 359, 32, 26, 0x00, 32, 32 );
+  TEST_VSETCFGIVL( 360, 32, 26, 0x00, 33, 32 );
+  TEST_VSETCFGIVL( 361, 32, 26, 0x00, 31, 31 );
+
+  TEST_VSETCFGIVL( 362, 32, 27, 0xf8, 12, 12 );
+  TEST_VSETCFGIVL( 363, 32, 27, 0xf8, 13, 12 );
+  TEST_VSETCFGIVL( 364, 32, 27, 0xf8, 11, 11 );
+
+  TEST_VSETCFGIVL( 365, 32, 27, 0x00, 32, 32 );
+  TEST_VSETCFGIVL( 366, 32, 27, 0x00, 33, 32 );
+  TEST_VSETCFGIVL( 367, 32, 27, 0x00, 31, 31 );
+
+  TEST_VSETCFGIVL( 368, 32, 28, 0xf8, 12, 12 );
+  TEST_VSETCFGIVL( 369, 32, 28, 0xf8, 13, 12 );
+  TEST_VSETCFGIVL( 370, 32, 28, 0xf8, 11, 11 );
+
+  TEST_VSETCFGIVL( 371, 32, 28, 0x00, 32, 32 );
+  TEST_VSETCFGIVL( 372, 32, 28, 0x00, 33, 32 );
+  TEST_VSETCFGIVL( 373, 32, 28, 0x00, 31, 31 );
+
+  TEST_VSETCFGIVL( 374, 32, 29, 0xf8, 12, 12 );
+  TEST_VSETCFGIVL( 375, 32, 29, 0xf8, 13, 12 );
+  TEST_VSETCFGIVL( 376, 32, 29, 0xf8, 11, 11 );
+
+  TEST_VSETCFGIVL( 377, 32, 29, 0x00, 32, 32 );
+  TEST_VSETCFGIVL( 378, 32, 29, 0x00, 33, 32 );
+  TEST_VSETCFGIVL( 379, 32, 29, 0x00, 31, 31 );
+
+  TEST_VSETCFGIVL( 380, 32, 30, 0xf8, 12, 12 );
+  TEST_VSETCFGIVL( 381, 32, 30, 0xf8, 13, 12 );
+  TEST_VSETCFGIVL( 382, 32, 30, 0xf8, 11, 11 );
+
+  TEST_VSETCFGIVL( 383, 32, 30, 0x00, 32, 32 );
+  TEST_VSETCFGIVL( 384, 32, 30, 0x00, 33, 32 );
+  TEST_VSETCFGIVL( 385, 32, 30, 0x00, 31, 31 );
+
+  TEST_VSETCFGIVL( 386, 32, 31, 0xf8, 12, 12 );
+  TEST_VSETCFGIVL( 387, 32, 31, 0xf8, 13, 12 );
+  TEST_VSETCFGIVL( 388, 32, 31, 0xf8, 11, 11 );
+
+  TEST_VSETCFGIVL( 389, 32, 31, 0x00, 32, 32 );
+  TEST_VSETCFGIVL( 390, 32, 31, 0x00, 33, 32 );
+  TEST_VSETCFGIVL( 391, 32, 31, 0x00, 31, 31 );
+
+  TEST_VSETCFGIVL( 392, 32, 32, 0xf8, 12, 12 );
+  TEST_VSETCFGIVL( 393, 32, 32, 0xf8, 13, 12 );
+  TEST_VSETCFGIVL( 394, 32, 32, 0xf8, 11, 11 );
+
+  TEST_VSETCFGIVL( 395, 32, 32, 0x00, 32, 32 );
+  TEST_VSETCFGIVL( 396, 32, 32, 0x00, 33, 32 );
+  TEST_VSETCFGIVL( 397, 32, 32, 0x00, 31, 31 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END

diff --git a/isa/rv64uv/vsetvl.S b/isa/rv64uv/vsetvl.S
index 862e983d9d894d4c2c2e44378d19e3054a1a3427..05235e891956e3c222bb12c80e3c446b1a717062 100644 (file)
--- a/isa/rv64uv/vsetvl.S
+++ b/isa/rv64uv/vsetvl.S
@@ -15,533 +15,533 @@ RVTEST_CODE_BEGIN
   # Arithmetic tests
   #-------------------------------------------------------------
 
-  TEST_VSETVL( 2, 0, 0, 0x07, 768, 768 );
-  TEST_VSETVL( 3, 0, 0, 0x07, 769, 768 );
-  TEST_VSETVL( 4, 0, 0, 0x07, 767, 767 );
+  TEST_VSETVL( 2, 0, 0, 0xf8, 768, 768 );
+  TEST_VSETVL( 3, 0, 0, 0xf8, 769, 768 );
+  TEST_VSETVL( 4, 0, 0, 0xf8, 767, 767 );
 
-  TEST_VSETVL( 5, 0, 0, 0xff, 2048, 2048 );
-  TEST_VSETVL( 6, 0, 0, 0xff, 2049, 2048 );
-  TEST_VSETVL( 7, 0, 0, 0xff, 2047, 2047 );
+  TEST_VSETVL( 5, 0, 0, 0x00, 2048, 2048 );
+  TEST_VSETVL( 6, 0, 0, 0x00, 2049, 2048 );
+  TEST_VSETVL( 7, 0, 0, 0x00, 2047, 2047 );
 
-  TEST_VSETVL( 8, 1, 0, 0x07, 768, 768 );
-  TEST_VSETVL( 9, 1, 0, 0x07, 769, 768 );
-  TEST_VSETVL( 10, 1, 0, 0x07, 767, 767 );
+  TEST_VSETVL( 8, 1, 0, 0xf8, 768, 768 );
+  TEST_VSETVL( 9, 1, 0, 0xf8, 769, 768 );
+  TEST_VSETVL( 10, 1, 0, 0xf8, 767, 767 );
 
-  TEST_VSETVL( 11, 1, 0, 0xff, 2048, 2048 );
-  TEST_VSETVL( 12, 1, 0, 0xff, 2049, 2048 );
-  TEST_VSETVL( 13, 1, 0, 0xff, 2047, 2047 );
+  TEST_VSETVL( 11, 1, 0, 0x00, 2048, 2048 );
+  TEST_VSETVL( 12, 1, 0, 0x00, 2049, 2048 );
+  TEST_VSETVL( 13, 1, 0, 0x00, 2047, 2047 );
 
-  TEST_VSETVL( 14, 2, 0, 0x07, 768, 768 );
-  TEST_VSETVL( 15, 2, 0, 0x07, 769, 768 );
-  TEST_VSETVL( 16, 2, 0, 0x07, 767, 767 );
+  TEST_VSETVL( 14, 2, 0, 0xf8, 768, 768 );
+  TEST_VSETVL( 15, 2, 0, 0xf8, 769, 768 );
+  TEST_VSETVL( 16, 2, 0, 0xf8, 767, 767 );
 
-  TEST_VSETVL( 17, 2, 0, 0xff, 2048, 2048 );
-  TEST_VSETVL( 18, 2, 0, 0xff, 2049, 2048 );
-  TEST_VSETVL( 19, 2, 0, 0xff, 2047, 2047 );
+  TEST_VSETVL( 17, 2, 0, 0x00, 2048, 2048 );
+  TEST_VSETVL( 18, 2, 0, 0x00, 2049, 2048 );
+  TEST_VSETVL( 19, 2, 0, 0x00, 2047, 2047 );
 
-  TEST_VSETVL( 20, 3, 0, 0x07, 384, 384 );
-  TEST_VSETVL( 21, 3, 0, 0x07, 385, 384 );
-  TEST_VSETVL( 22, 3, 0, 0x07, 383, 383 );
+  TEST_VSETVL( 20, 3, 0, 0xf8, 384, 384 );
+  TEST_VSETVL( 21, 3, 0, 0xf8, 385, 384 );
+  TEST_VSETVL( 22, 3, 0, 0xf8, 383, 383 );
 
-  TEST_VSETVL( 23, 3, 0, 0xff, 1024, 1024 );
-  TEST_VSETVL( 24, 3, 0, 0xff, 1025, 1024 );
-  TEST_VSETVL( 25, 3, 0, 0xff, 1023, 1023 );
+  TEST_VSETVL( 23, 3, 0, 0x00, 1024, 1024 );
+  TEST_VSETVL( 24, 3, 0, 0x00, 1025, 1024 );
+  TEST_VSETVL( 25, 3, 0, 0x00, 1023, 1023 );
 
-  TEST_VSETVL( 26, 4, 0, 0x07, 255, 255 );
-  TEST_VSETVL( 27, 4, 0, 0x07, 256, 255 );
-  TEST_VSETVL( 28, 4, 0, 0x07, 254, 254 );
+  TEST_VSETVL( 26, 4, 0, 0xf8, 255, 255 );
+  TEST_VSETVL( 27, 4, 0, 0xf8, 256, 255 );
+  TEST_VSETVL( 28, 4, 0, 0xf8, 254, 254 );
 
-  TEST_VSETVL( 29, 4, 0, 0xff, 680, 680 );
-  TEST_VSETVL( 30, 4, 0, 0xff, 681, 680 );
-  TEST_VSETVL( 31, 4, 0, 0xff, 679, 679 );
+  TEST_VSETVL( 29, 4, 0, 0x00, 680, 680 );
+  TEST_VSETVL( 30, 4, 0, 0x00, 681, 680 );
+  TEST_VSETVL( 31, 4, 0, 0x00, 679, 679 );
 
-  TEST_VSETVL( 32, 5, 0, 0x07, 192, 192 );
-  TEST_VSETVL( 33, 5, 0, 0x07, 193, 192 );
-  TEST_VSETVL( 34, 5, 0, 0x07, 191, 191 );
+  TEST_VSETVL( 32, 5, 0, 0xf8, 192, 192 );
+  TEST_VSETVL( 33, 5, 0, 0xf8, 193, 192 );
+  TEST_VSETVL( 34, 5, 0, 0xf8, 191, 191 );
 
-  TEST_VSETVL( 35, 5, 0, 0xff, 512, 512 );
-  TEST_VSETVL( 36, 5, 0, 0xff, 513, 512 );
-  TEST_VSETVL( 37, 5, 0, 0xff, 511, 511 );
+  TEST_VSETVL( 35, 5, 0, 0x00, 512, 512 );
+  TEST_VSETVL( 36, 5, 0, 0x00, 513, 512 );
+  TEST_VSETVL( 37, 5, 0, 0x00, 511, 511 );
 
-  TEST_VSETVL( 38, 6, 0, 0x07, 153, 153 );
-  TEST_VSETVL( 39, 6, 0, 0x07, 154, 153 );
-  TEST_VSETVL( 40, 6, 0, 0x07, 152, 152 );
+  TEST_VSETVL( 38, 6, 0, 0xf8, 153, 153 );
+  TEST_VSETVL( 39, 6, 0, 0xf8, 154, 153 );
+  TEST_VSETVL( 40, 6, 0, 0xf8, 152, 152 );
 
-  TEST_VSETVL( 41, 6, 0, 0xff, 408, 408 );
-  TEST_VSETVL( 42, 6, 0, 0xff, 409, 408 );
-  TEST_VSETVL( 43, 6, 0, 0xff, 407, 407 );
+  TEST_VSETVL( 41, 6, 0, 0x00, 408, 408 );
+  TEST_VSETVL( 42, 6, 0, 0x00, 409, 408 );
+  TEST_VSETVL( 43, 6, 0, 0x00, 407, 407 );
 
-  TEST_VSETVL( 44, 7, 0, 0x07, 126, 126 );
-  TEST_VSETVL( 45, 7, 0, 0x07, 127, 126 );
-  TEST_VSETVL( 46, 7, 0, 0x07, 125, 125 );
+  TEST_VSETVL( 44, 7, 0, 0xf8, 126, 126 );
+  TEST_VSETVL( 45, 7, 0, 0xf8, 127, 126 );
+  TEST_VSETVL( 46, 7, 0, 0xf8, 125, 125 );
 
-  TEST_VSETVL( 47, 7, 0, 0xff, 336, 336 );
-  TEST_VSETVL( 48, 7, 0, 0xff, 337, 336 );
-  TEST_VSETVL( 49, 7, 0, 0xff, 335, 335 );
+  TEST_VSETVL( 47, 7, 0, 0x00, 336, 336 );
+  TEST_VSETVL( 48, 7, 0, 0x00, 337, 336 );
+  TEST_VSETVL( 49, 7, 0, 0x00, 335, 335 );
 
-  TEST_VSETVL( 50, 8, 0, 0x07, 108, 108 );
-  TEST_VSETVL( 51, 8, 0, 0x07, 109, 108 );
-  TEST_VSETVL( 52, 8, 0, 0x07, 107, 107 );
+  TEST_VSETVL( 50, 8, 0, 0xf8, 108, 108 );
+  TEST_VSETVL( 51, 8, 0, 0xf8, 109, 108 );
+  TEST_VSETVL( 52, 8, 0, 0xf8, 107, 107 );
 
-  TEST_VSETVL( 53, 8, 0, 0xff, 288, 288 );
-  TEST_VSETVL( 54, 8, 0, 0xff, 289, 288 );
-  TEST_VSETVL( 55, 8, 0, 0xff, 287, 287 );
+  TEST_VSETVL( 53, 8, 0, 0x00, 288, 288 );
+  TEST_VSETVL( 54, 8, 0, 0x00, 289, 288 );
+  TEST_VSETVL( 55, 8, 0, 0x00, 287, 287 );
 
-  TEST_VSETVL( 56, 9, 0, 0x07, 96, 96 );
-  TEST_VSETVL( 57, 9, 0, 0x07, 97, 96 );
-  TEST_VSETVL( 58, 9, 0, 0x07, 95, 95 );
+  TEST_VSETVL( 56, 9, 0, 0xf8, 96, 96 );
+  TEST_VSETVL( 57, 9, 0, 0xf8, 97, 96 );
+  TEST_VSETVL( 58, 9, 0, 0xf8, 95, 95 );
 
-  TEST_VSETVL( 59, 9, 0, 0xff, 256, 256 );
-  TEST_VSETVL( 60, 9, 0, 0xff, 257, 256 );
-  TEST_VSETVL( 61, 9, 0, 0xff, 255, 255 );
+  TEST_VSETVL( 59, 9, 0, 0x00, 256, 256 );
+  TEST_VSETVL( 60, 9, 0, 0x00, 257, 256 );
+  TEST_VSETVL( 61, 9, 0, 0x00, 255, 255 );
 
-  TEST_VSETVL( 62, 10, 0, 0x07, 84, 84 );
-  TEST_VSETVL( 63, 10, 0, 0x07, 85, 84 );
-  TEST_VSETVL( 64, 10, 0, 0x07, 83, 83 );
+  TEST_VSETVL( 62, 10, 0, 0xf8, 84, 84 );
+  TEST_VSETVL( 63, 10, 0, 0xf8, 85, 84 );
+  TEST_VSETVL( 64, 10, 0, 0xf8, 83, 83 );
 
-  TEST_VSETVL( 65, 10, 0, 0xff, 224, 224 );
-  TEST_VSETVL( 66, 10, 0, 0xff, 225, 224 );
-  TEST_VSETVL( 67, 10, 0, 0xff, 223, 223 );
+  TEST_VSETVL( 65, 10, 0, 0x00, 224, 224 );
+  TEST_VSETVL( 66, 10, 0, 0x00, 225, 224 );
+  TEST_VSETVL( 67, 10, 0, 0x00, 223, 223 );
 
-  TEST_VSETVL( 68, 11, 0, 0x07, 75, 75 );
-  TEST_VSETVL( 69, 11, 0, 0x07, 76, 75 );
-  TEST_VSETVL( 70, 11, 0, 0x07, 74, 74 );
+  TEST_VSETVL( 68, 11, 0, 0xf8, 75, 75 );
+  TEST_VSETVL( 69, 11, 0, 0xf8, 76, 75 );
+  TEST_VSETVL( 70, 11, 0, 0xf8, 74, 74 );
 
-  TEST_VSETVL( 71, 11, 0, 0xff, 200, 200 );
-  TEST_VSETVL( 72, 11, 0, 0xff, 201, 200 );
-  TEST_VSETVL( 73, 11, 0, 0xff, 199, 199 );
+  TEST_VSETVL( 71, 11, 0, 0x00, 200, 200 );
+  TEST_VSETVL( 72, 11, 0, 0x00, 201, 200 );
+  TEST_VSETVL( 73, 11, 0, 0x00, 199, 199 );
 
-  TEST_VSETVL( 74, 12, 0, 0x07, 69, 69 );
-  TEST_VSETVL( 75, 12, 0, 0x07, 70, 69 );
-  TEST_VSETVL( 76, 12, 0, 0x07, 68, 68 );
+  TEST_VSETVL( 74, 12, 0, 0xf8, 69, 69 );
+  TEST_VSETVL( 75, 12, 0, 0xf8, 70, 69 );
+  TEST_VSETVL( 76, 12, 0, 0xf8, 68, 68 );
 
-  TEST_VSETVL( 77, 12, 0, 0xff, 184, 184 );
-  TEST_VSETVL( 78, 12, 0, 0xff, 185, 184 );
-  TEST_VSETVL( 79, 12, 0, 0xff, 183, 183 );
+  TEST_VSETVL( 77, 12, 0, 0x00, 184, 184 );
+  TEST_VSETVL( 78, 12, 0, 0x00, 185, 184 );
+  TEST_VSETVL( 79, 12, 0, 0x00, 183, 183 );
 
-  TEST_VSETVL( 80, 13, 0, 0x07, 63, 63 );
-  TEST_VSETVL( 81, 13, 0, 0x07, 64, 63 );
-  TEST_VSETVL( 82, 13, 0, 0x07, 62, 62 );
+  TEST_VSETVL( 80, 13, 0, 0xf8, 63, 63 );
+  TEST_VSETVL( 81, 13, 0, 0xf8, 64, 63 );
+  TEST_VSETVL( 82, 13, 0, 0xf8, 62, 62 );
 
-  TEST_VSETVL( 83, 13, 0, 0xff, 168, 168 );
-  TEST_VSETVL( 84, 13, 0, 0xff, 169, 168 );
-  TEST_VSETVL( 85, 13, 0, 0xff, 167, 167 );
+  TEST_VSETVL( 83, 13, 0, 0x00, 168, 168 );
+  TEST_VSETVL( 84, 13, 0, 0x00, 169, 168 );
+  TEST_VSETVL( 85, 13, 0, 0x00, 167, 167 );
 
-  TEST_VSETVL( 86, 14, 0, 0x07, 57, 57 );
-  TEST_VSETVL( 87, 14, 0, 0x07, 58, 57 );
-  TEST_VSETVL( 88, 14, 0, 0x07, 56, 56 );
+  TEST_VSETVL( 86, 14, 0, 0xf8, 57, 57 );
+  TEST_VSETVL( 87, 14, 0, 0xf8, 58, 57 );
+  TEST_VSETVL( 88, 14, 0, 0xf8, 56, 56 );
 
-  TEST_VSETVL( 89, 14, 0, 0xff, 152, 152 );
-  TEST_VSETVL( 90, 14, 0, 0xff, 153, 152 );
-  TEST_VSETVL( 91, 14, 0, 0xff, 151, 151 );
+  TEST_VSETVL( 89, 14, 0, 0x00, 152, 152 );
+  TEST_VSETVL( 90, 14, 0, 0x00, 153, 152 );
+  TEST_VSETVL( 91, 14, 0, 0x00, 151, 151 );
 
-  TEST_VSETVL( 92, 15, 0, 0x07, 54, 54 );
-  TEST_VSETVL( 93, 15, 0, 0x07, 55, 54 );
-  TEST_VSETVL( 94, 15, 0, 0x07, 53, 53 );
+  TEST_VSETVL( 92, 15, 0, 0xf8, 54, 54 );
+  TEST_VSETVL( 93, 15, 0, 0xf8, 55, 54 );
+  TEST_VSETVL( 94, 15, 0, 0xf8, 53, 53 );
 
-  TEST_VSETVL( 95, 15, 0, 0xff, 144, 144 );
-  TEST_VSETVL( 96, 15, 0, 0xff, 145, 144 );
-  TEST_VSETVL( 97, 15, 0, 0xff, 143, 143 );
+  TEST_VSETVL( 95, 15, 0, 0x00, 144, 144 );
+  TEST_VSETVL( 96, 15, 0, 0x00, 145, 144 );
+  TEST_VSETVL( 97, 15, 0, 0x00, 143, 143 );
 
-  TEST_VSETVL( 98, 16, 0, 0x07, 51, 51 );
-  TEST_VSETVL( 99, 16, 0, 0x07, 52, 51 );
-  TEST_VSETVL( 100, 16, 0, 0x07, 50, 50 );
+  TEST_VSETVL( 98, 16, 0, 0xf8, 51, 51 );
+  TEST_VSETVL( 99, 16, 0, 0xf8, 52, 51 );
+  TEST_VSETVL( 100, 16, 0, 0xf8, 50, 50 );
 
-  TEST_VSETVL( 101, 16, 0, 0xff, 136, 136 );
-  TEST_VSETVL( 102, 16, 0, 0xff, 137, 136 );
-  TEST_VSETVL( 103, 16, 0, 0xff, 135, 135 );
+  TEST_VSETVL( 101, 16, 0, 0x00, 136, 136 );
+  TEST_VSETVL( 102, 16, 0, 0x00, 137, 136 );
+  TEST_VSETVL( 103, 16, 0, 0x00, 135, 135 );
 
-  TEST_VSETVL( 104, 17, 0, 0x07, 48, 48 );
-  TEST_VSETVL( 105, 17, 0, 0x07, 49, 48 );
-  TEST_VSETVL( 106, 17, 0, 0x07, 47, 47 );
+  TEST_VSETVL( 104, 17, 0, 0xf8, 48, 48 );
+  TEST_VSETVL( 105, 17, 0, 0xf8, 49, 48 );
+  TEST_VSETVL( 106, 17, 0, 0xf8, 47, 47 );
 
-  TEST_VSETVL( 107, 17, 0, 0xff, 128, 128 );
-  TEST_VSETVL( 108, 17, 0, 0xff, 129, 128 );
-  TEST_VSETVL( 109, 17, 0, 0xff, 127, 127 );
+  TEST_VSETVL( 107, 17, 0, 0x00, 128, 128 );
+  TEST_VSETVL( 108, 17, 0, 0x00, 129, 128 );
+  TEST_VSETVL( 109, 17, 0, 0x00, 127, 127 );
 
-  TEST_VSETVL( 110, 18, 0, 0x07, 45, 45 );
-  TEST_VSETVL( 111, 18, 0, 0x07, 46, 45 );
-  TEST_VSETVL( 112, 18, 0, 0x07, 44, 44 );
+  TEST_VSETVL( 110, 18, 0, 0xf8, 45, 45 );
+  TEST_VSETVL( 111, 18, 0, 0xf8, 46, 45 );
+  TEST_VSETVL( 112, 18, 0, 0xf8, 44, 44 );
 
-  TEST_VSETVL( 113, 18, 0, 0xff, 120, 120 );
-  TEST_VSETVL( 114, 18, 0, 0xff, 121, 120 );
-  TEST_VSETVL( 115, 18, 0, 0xff, 119, 119 );
+  TEST_VSETVL( 113, 18, 0, 0x00, 120, 120 );
+  TEST_VSETVL( 114, 18, 0, 0x00, 121, 120 );
+  TEST_VSETVL( 115, 18, 0, 0x00, 119, 119 );
 
-  TEST_VSETVL( 116, 19, 0, 0x07, 42, 42 );
-  TEST_VSETVL( 117, 19, 0, 0x07, 43, 42 );
-  TEST_VSETVL( 118, 19, 0, 0x07, 41, 41 );
+  TEST_VSETVL( 116, 19, 0, 0xf8, 42, 42 );
+  TEST_VSETVL( 117, 19, 0, 0xf8, 43, 42 );
+  TEST_VSETVL( 118, 19, 0, 0xf8, 41, 41 );
 
-  TEST_VSETVL( 119, 19, 0, 0xff, 112, 112 );
-  TEST_VSETVL( 120, 19, 0, 0xff, 113, 112 );
-  TEST_VSETVL( 121, 19, 0, 0xff, 111, 111 );
+  TEST_VSETVL( 119, 19, 0, 0x00, 112, 112 );
+  TEST_VSETVL( 120, 19, 0, 0x00, 113, 112 );
+  TEST_VSETVL( 121, 19, 0, 0x00, 111, 111 );
 
-  TEST_VSETVL( 122, 20, 0, 0x07, 39, 39 );
-  TEST_VSETVL( 123, 20, 0, 0x07, 40, 39 );
-  TEST_VSETVL( 124, 20, 0, 0x07, 38, 38 );
+  TEST_VSETVL( 122, 20, 0, 0xf8, 39, 39 );
+  TEST_VSETVL( 123, 20, 0, 0xf8, 40, 39 );
+  TEST_VSETVL( 124, 20, 0, 0xf8, 38, 38 );
 
-  TEST_VSETVL( 125, 20, 0, 0xff, 104, 104 );
-  TEST_VSETVL( 126, 20, 0, 0xff, 105, 104 );
-  TEST_VSETVL( 127, 20, 0, 0xff, 103, 103 );
+  TEST_VSETVL( 125, 20, 0, 0x00, 104, 104 );
+  TEST_VSETVL( 126, 20, 0, 0x00, 105, 104 );
+  TEST_VSETVL( 127, 20, 0, 0x00, 103, 103 );
 
-  TEST_VSETVL( 128, 21, 0, 0x07, 36, 36 );
-  TEST_VSETVL( 129, 21, 0, 0x07, 37, 36 );
-  TEST_VSETVL( 130, 21, 0, 0x07, 35, 35 );
+  TEST_VSETVL( 128, 21, 0, 0xf8, 36, 36 );
+  TEST_VSETVL( 129, 21, 0, 0xf8, 37, 36 );
+  TEST_VSETVL( 130, 21, 0, 0xf8, 35, 35 );
 
-  TEST_VSETVL( 131, 21, 0, 0xff, 96, 96 );
-  TEST_VSETVL( 132, 21, 0, 0xff, 97, 96 );
-  TEST_VSETVL( 133, 21, 0, 0xff, 95, 95 );
+  TEST_VSETVL( 131, 21, 0, 0x00, 96, 96 );
+  TEST_VSETVL( 132, 21, 0, 0x00, 97, 96 );
+  TEST_VSETVL( 133, 21, 0, 0x00, 95, 95 );
 
-  TEST_VSETVL( 134, 22, 0, 0x07, 36, 36 );
-  TEST_VSETVL( 135, 22, 0, 0x07, 37, 36 );
-  TEST_VSETVL( 136, 22, 0, 0x07, 35, 35 );
+  TEST_VSETVL( 134, 22, 0, 0xf8, 36, 36 );
+  TEST_VSETVL( 135, 22, 0, 0xf8, 37, 36 );
+  TEST_VSETVL( 136, 22, 0, 0xf8, 35, 35 );
 
-  TEST_VSETVL( 137, 22, 0, 0xff, 96, 96 );
-  TEST_VSETVL( 138, 22, 0, 0xff, 97, 96 );
-  TEST_VSETVL( 139, 22, 0, 0xff, 95, 95 );
+  TEST_VSETVL( 137, 22, 0, 0x00, 96, 96 );
+  TEST_VSETVL( 138, 22, 0, 0x00, 97, 96 );
+  TEST_VSETVL( 139, 22, 0, 0x00, 95, 95 );
 
-  TEST_VSETVL( 140, 23, 0, 0x07, 33, 33 );
-  TEST_VSETVL( 141, 23, 0, 0x07, 34, 33 );
-  TEST_VSETVL( 142, 23, 0, 0x07, 32, 32 );
+  TEST_VSETVL( 140, 23, 0, 0xf8, 33, 33 );
+  TEST_VSETVL( 141, 23, 0, 0xf8, 34, 33 );
+  TEST_VSETVL( 142, 23, 0, 0xf8, 32, 32 );
 
-  TEST_VSETVL( 143, 23, 0, 0xff, 88, 88 );
-  TEST_VSETVL( 144, 23, 0, 0xff, 89, 88 );
-  TEST_VSETVL( 145, 23, 0, 0xff, 87, 87 );
+  TEST_VSETVL( 143, 23, 0, 0x00, 88, 88 );
+  TEST_VSETVL( 144, 23, 0, 0x00, 89, 88 );
+  TEST_VSETVL( 145, 23, 0, 0x00, 87, 87 );
 
-  TEST_VSETVL( 146, 24, 0, 0x07, 33, 33 );
-  TEST_VSETVL( 147, 24, 0, 0x07, 34, 33 );
-  TEST_VSETVL( 148, 24, 0, 0x07, 32, 32 );
+  TEST_VSETVL( 146, 24, 0, 0xf8, 33, 33 );
+  TEST_VSETVL( 147, 24, 0, 0xf8, 34, 33 );
+  TEST_VSETVL( 148, 24, 0, 0xf8, 32, 32 );
 
-  TEST_VSETVL( 149, 24, 0, 0xff, 88, 88 );
-  TEST_VSETVL( 150, 24, 0, 0xff, 89, 88 );
-  TEST_VSETVL( 151, 24, 0, 0xff, 87, 87 );
+  TEST_VSETVL( 149, 24, 0, 0x00, 88, 88 );
+  TEST_VSETVL( 150, 24, 0, 0x00, 89, 88 );
+  TEST_VSETVL( 151, 24, 0, 0x00, 87, 87 );
 
-  TEST_VSETVL( 152, 25, 0, 0x07, 30, 30 );
-  TEST_VSETVL( 153, 25, 0, 0x07, 31, 30 );
-  TEST_VSETVL( 154, 25, 0, 0x07, 29, 29 );
+  TEST_VSETVL( 152, 25, 0, 0xf8, 30, 30 );
+  TEST_VSETVL( 153, 25, 0, 0xf8, 31, 30 );
+  TEST_VSETVL( 154, 25, 0, 0xf8, 29, 29 );
 
-  TEST_VSETVL( 155, 25, 0, 0xff, 80, 80 );
-  TEST_VSETVL( 156, 25, 0, 0xff, 81, 80 );
-  TEST_VSETVL( 157, 25, 0, 0xff, 79, 79 );
+  TEST_VSETVL( 155, 25, 0, 0x00, 80, 80 );
+  TEST_VSETVL( 156, 25, 0, 0x00, 81, 80 );
+  TEST_VSETVL( 157, 25, 0, 0x00, 79, 79 );
 
-  TEST_VSETVL( 158, 26, 0, 0x07, 30, 30 );
-  TEST_VSETVL( 159, 26, 0, 0x07, 31, 30 );
-  TEST_VSETVL( 160, 26, 0, 0x07, 29, 29 );
+  TEST_VSETVL( 158, 26, 0, 0xf8, 30, 30 );
+  TEST_VSETVL( 159, 26, 0, 0xf8, 31, 30 );
+  TEST_VSETVL( 160, 26, 0, 0xf8, 29, 29 );
 
-  TEST_VSETVL( 161, 26, 0, 0xff, 80, 80 );
-  TEST_VSETVL( 162, 26, 0, 0xff, 81, 80 );
-  TEST_VSETVL( 163, 26, 0, 0xff, 79, 79 );
+  TEST_VSETVL( 161, 26, 0, 0x00, 80, 80 );
+  TEST_VSETVL( 162, 26, 0, 0x00, 81, 80 );
+  TEST_VSETVL( 163, 26, 0, 0x00, 79, 79 );
 
-  TEST_VSETVL( 164, 27, 0, 0x07, 27, 27 );
-  TEST_VSETVL( 165, 27, 0, 0x07, 28, 27 );
-  TEST_VSETVL( 166, 27, 0, 0x07, 26, 26 );
+  TEST_VSETVL( 164, 27, 0, 0xf8, 27, 27 );
+  TEST_VSETVL( 165, 27, 0, 0xf8, 28, 27 );
+  TEST_VSETVL( 166, 27, 0, 0xf8, 26, 26 );
 
-  TEST_VSETVL( 167, 27, 0, 0xff, 72, 72 );
-  TEST_VSETVL( 168, 27, 0, 0xff, 73, 72 );
-  TEST_VSETVL( 169, 27, 0, 0xff, 71, 71 );
+  TEST_VSETVL( 167, 27, 0, 0x00, 72, 72 );
+  TEST_VSETVL( 168, 27, 0, 0x00, 73, 72 );
+  TEST_VSETVL( 169, 27, 0, 0x00, 71, 71 );
 
-  TEST_VSETVL( 170, 28, 0, 0x07, 27, 27 );
-  TEST_VSETVL( 171, 28, 0, 0x07, 28, 27 );
-  TEST_VSETVL( 172, 28, 0, 0x07, 26, 26 );
+  TEST_VSETVL( 170, 28, 0, 0xf8, 27, 27 );
+  TEST_VSETVL( 171, 28, 0, 0xf8, 28, 27 );
+  TEST_VSETVL( 172, 28, 0, 0xf8, 26, 26 );
 
-  TEST_VSETVL( 173, 28, 0, 0xff, 72, 72 );
-  TEST_VSETVL( 174, 28, 0, 0xff, 73, 72 );
-  TEST_VSETVL( 175, 28, 0, 0xff, 71, 71 );
+  TEST_VSETVL( 173, 28, 0, 0x00, 72, 72 );
+  TEST_VSETVL( 174, 28, 0, 0x00, 73, 72 );
+  TEST_VSETVL( 175, 28, 0, 0x00, 71, 71 );
 
-  TEST_VSETVL( 176, 29, 0, 0x07, 27, 27 );
-  TEST_VSETVL( 177, 29, 0, 0x07, 28, 27 );
-  TEST_VSETVL( 178, 29, 0, 0x07, 26, 26 );
+  TEST_VSETVL( 176, 29, 0, 0xf8, 27, 27 );
+  TEST_VSETVL( 177, 29, 0, 0xf8, 28, 27 );
+  TEST_VSETVL( 178, 29, 0, 0xf8, 26, 26 );
 
-  TEST_VSETVL( 179, 29, 0, 0xff, 72, 72 );
-  TEST_VSETVL( 180, 29, 0, 0xff, 73, 72 );
-  TEST_VSETVL( 181, 29, 0, 0xff, 71, 71 );
+  TEST_VSETVL( 179, 29, 0, 0x00, 72, 72 );
+  TEST_VSETVL( 180, 29, 0, 0x00, 73, 72 );
+  TEST_VSETVL( 181, 29, 0, 0x00, 71, 71 );
 
-  TEST_VSETVL( 182, 30, 0, 0x07, 24, 24 );
-  TEST_VSETVL( 183, 30, 0, 0x07, 25, 24 );
-  TEST_VSETVL( 184, 30, 0, 0x07, 23, 23 );
+  TEST_VSETVL( 182, 30, 0, 0xf8, 24, 24 );
+  TEST_VSETVL( 183, 30, 0, 0xf8, 25, 24 );
+  TEST_VSETVL( 184, 30, 0, 0xf8, 23, 23 );
 
-  TEST_VSETVL( 185, 30, 0, 0xff, 64, 64 );
-  TEST_VSETVL( 186, 30, 0, 0xff, 65, 64 );
-  TEST_VSETVL( 187, 30, 0, 0xff, 63, 63 );
+  TEST_VSETVL( 185, 30, 0, 0x00, 64, 64 );
+  TEST_VSETVL( 186, 30, 0, 0x00, 65, 64 );
+  TEST_VSETVL( 187, 30, 0, 0x00, 63, 63 );
 
-  TEST_VSETVL( 188, 31, 0, 0x07, 24, 24 );
-  TEST_VSETVL( 189, 31, 0, 0x07, 25, 24 );
-  TEST_VSETVL( 190, 31, 0, 0x07, 23, 23 );
+  TEST_VSETVL( 188, 31, 0, 0xf8, 24, 24 );
+  TEST_VSETVL( 189, 31, 0, 0xf8, 25, 24 );
+  TEST_VSETVL( 190, 31, 0, 0xf8, 23, 23 );
 
-  TEST_VSETVL( 191, 31, 0, 0xff, 64, 64 );
-  TEST_VSETVL( 192, 31, 0, 0xff, 65, 64 );
-  TEST_VSETVL( 193, 31, 0, 0xff, 63, 63 );
+  TEST_VSETVL( 191, 31, 0, 0x00, 64, 64 );
+  TEST_VSETVL( 192, 31, 0, 0x00, 65, 64 );
+  TEST_VSETVL( 193, 31, 0, 0x00, 63, 63 );
 
-  TEST_VSETVL( 194, 32, 0, 0x07, 24, 24 );
-  TEST_VSETVL( 195, 32, 0, 0x07, 25, 24 );
-  TEST_VSETVL( 196, 32, 0, 0x07, 23, 23 );
+  TEST_VSETVL( 194, 32, 0, 0xf8, 24, 24 );
+  TEST_VSETVL( 195, 32, 0, 0xf8, 25, 24 );
+  TEST_VSETVL( 196, 32, 0, 0xf8, 23, 23 );
 
-  TEST_VSETVL( 197, 32, 0, 0xff, 64, 64 );
-  TEST_VSETVL( 198, 32, 0, 0xff, 65, 64 );
-  TEST_VSETVL( 199, 32, 0, 0xff, 63, 63 );
+  TEST_VSETVL( 197, 32, 0, 0x00, 64, 64 );
+  TEST_VSETVL( 198, 32, 0, 0x00, 65, 64 );
+  TEST_VSETVL( 199, 32, 0, 0x00, 63, 63 );
 
-  TEST_VSETVL( 200, 32, 0, 0x07, 24, 24 );
-  TEST_VSETVL( 201, 32, 0, 0x07, 25, 24 );
-  TEST_VSETVL( 202, 32, 0, 0x07, 23, 23 );
+  TEST_VSETVL( 200, 32, 0, 0xf8, 24, 24 );
+  TEST_VSETVL( 201, 32, 0, 0xf8, 25, 24 );
+  TEST_VSETVL( 202, 32, 0, 0xf8, 23, 23 );
 
-  TEST_VSETVL( 203, 32, 0, 0xff, 64, 64 );
-  TEST_VSETVL( 204, 32, 0, 0xff, 65, 64 );
-  TEST_VSETVL( 205, 32, 0, 0xff, 63, 63 );
+  TEST_VSETVL( 203, 32, 0, 0x00, 64, 64 );
+  TEST_VSETVL( 204, 32, 0, 0x00, 65, 64 );
+  TEST_VSETVL( 205, 32, 0, 0x00, 63, 63 );
 
-  TEST_VSETVL( 206, 32, 1, 0x07, 24, 24 );
-  TEST_VSETVL( 207, 32, 1, 0x07, 25, 24 );
-  TEST_VSETVL( 208, 32, 1, 0x07, 23, 23 );
+  TEST_VSETVL( 206, 32, 1, 0xf8, 24, 24 );
+  TEST_VSETVL( 207, 32, 1, 0xf8, 25, 24 );
+  TEST_VSETVL( 208, 32, 1, 0xf8, 23, 23 );
 
-  TEST_VSETVL( 209, 32, 1, 0xff, 64, 64 );
-  TEST_VSETVL( 210, 32, 1, 0xff, 65, 64 );
-  TEST_VSETVL( 211, 32, 1, 0xff, 63, 63 );
+  TEST_VSETVL( 209, 32, 1, 0x00, 64, 64 );
+  TEST_VSETVL( 210, 32, 1, 0x00, 65, 64 );
+  TEST_VSETVL( 211, 32, 1, 0x00, 63, 63 );
 
-  TEST_VSETVL( 212, 32, 2, 0x07, 21, 21 );
-  TEST_VSETVL( 213, 32, 2, 0x07, 22, 21 );
-  TEST_VSETVL( 214, 32, 2, 0x07, 20, 20 );
+  TEST_VSETVL( 212, 32, 2, 0xf8, 21, 21 );
+  TEST_VSETVL( 213, 32, 2, 0xf8, 22, 21 );
+  TEST_VSETVL( 214, 32, 2, 0xf8, 20, 20 );
 
-  TEST_VSETVL( 215, 32, 2, 0xff, 56, 56 );
-  TEST_VSETVL( 216, 32, 2, 0xff, 57, 56 );
-  TEST_VSETVL( 217, 32, 2, 0xff, 55, 55 );
+  TEST_VSETVL( 215, 32, 2, 0x00, 56, 56 );
+  TEST_VSETVL( 216, 32, 2, 0x00, 57, 56 );
+  TEST_VSETVL( 217, 32, 2, 0x00, 55, 55 );
 
-  TEST_VSETVL( 218, 32, 3, 0x07, 21, 21 );
-  TEST_VSETVL( 219, 32, 3, 0x07, 22, 21 );
-  TEST_VSETVL( 220, 32, 3, 0x07, 20, 20 );
+  TEST_VSETVL( 218, 32, 3, 0xf8, 21, 21 );
+  TEST_VSETVL( 219, 32, 3, 0xf8, 22, 21 );
+  TEST_VSETVL( 220, 32, 3, 0xf8, 20, 20 );
 
-  TEST_VSETVL( 221, 32, 3, 0xff, 56, 56 );
-  TEST_VSETVL( 222, 32, 3, 0xff, 57, 56 );
-  TEST_VSETVL( 223, 32, 3, 0xff, 55, 55 );
+  TEST_VSETVL( 221, 32, 3, 0x00, 56, 56 );
+  TEST_VSETVL( 222, 32, 3, 0x00, 57, 56 );
+  TEST_VSETVL( 223, 32, 3, 0x00, 55, 55 );
 
-  TEST_VSETVL( 224, 32, 4, 0x07, 21, 21 );
-  TEST_VSETVL( 225, 32, 4, 0x07, 22, 21 );
-  TEST_VSETVL( 226, 32, 4, 0x07, 20, 20 );
+  TEST_VSETVL( 224, 32, 4, 0xf8, 21, 21 );
+  TEST_VSETVL( 225, 32, 4, 0xf8, 22, 21 );
+  TEST_VSETVL( 226, 32, 4, 0xf8, 20, 20 );
 
-  TEST_VSETVL( 227, 32, 4, 0xff, 56, 56 );
-  TEST_VSETVL( 228, 32, 4, 0xff, 57, 56 );
-  TEST_VSETVL( 229, 32, 4, 0xff, 55, 55 );
+  TEST_VSETVL( 227, 32, 4, 0x00, 56, 56 );
+  TEST_VSETVL( 228, 32, 4, 0x00, 57, 56 );
+  TEST_VSETVL( 229, 32, 4, 0x00, 55, 55 );
 
-  TEST_VSETVL( 230, 32, 5, 0x07, 21, 21 );
-  TEST_VSETVL( 231, 32, 5, 0x07, 22, 21 );
-  TEST_VSETVL( 232, 32, 5, 0x07, 20, 20 );
+  TEST_VSETVL( 230, 32, 5, 0xf8, 21, 21 );
+  TEST_VSETVL( 231, 32, 5, 0xf8, 22, 21 );
+  TEST_VSETVL( 232, 32, 5, 0xf8, 20, 20 );
 
-  TEST_VSETVL( 233, 32, 5, 0xff, 56, 56 );
-  TEST_VSETVL( 234, 32, 5, 0xff, 57, 56 );
-  TEST_VSETVL( 235, 32, 5, 0xff, 55, 55 );
+  TEST_VSETVL( 233, 32, 5, 0x00, 56, 56 );
+  TEST_VSETVL( 234, 32, 5, 0x00, 57, 56 );
+  TEST_VSETVL( 235, 32, 5, 0x00, 55, 55 );
 
-  TEST_VSETVL( 236, 32, 6, 0x07, 18, 18 );
-  TEST_VSETVL( 237, 32, 6, 0x07, 19, 18 );
-  TEST_VSETVL( 238, 32, 6, 0x07, 17, 17 );
+  TEST_VSETVL( 236, 32, 6, 0xf8, 18, 18 );
+  TEST_VSETVL( 237, 32, 6, 0xf8, 19, 18 );
+  TEST_VSETVL( 238, 32, 6, 0xf8, 17, 17 );
 
-  TEST_VSETVL( 239, 32, 6, 0xff, 48, 48 );
-  TEST_VSETVL( 240, 32, 6, 0xff, 49, 48 );
-  TEST_VSETVL( 241, 32, 6, 0xff, 47, 47 );
+  TEST_VSETVL( 239, 32, 6, 0x00, 48, 48 );
+  TEST_VSETVL( 240, 32, 6, 0x00, 49, 48 );
+  TEST_VSETVL( 241, 32, 6, 0x00, 47, 47 );
 
-  TEST_VSETVL( 242, 32, 7, 0x07, 18, 18 );
-  TEST_VSETVL( 243, 32, 7, 0x07, 19, 18 );
-  TEST_VSETVL( 244, 32, 7, 0x07, 17, 17 );
+  TEST_VSETVL( 242, 32, 7, 0xf8, 18, 18 );
+  TEST_VSETVL( 243, 32, 7, 0xf8, 19, 18 );
+  TEST_VSETVL( 244, 32, 7, 0xf8, 17, 17 );
 
-  TEST_VSETVL( 245, 32, 7, 0xff, 48, 48 );
-  TEST_VSETVL( 246, 32, 7, 0xff, 49, 48 );
-  TEST_VSETVL( 247, 32, 7, 0xff, 47, 47 );
+  TEST_VSETVL( 245, 32, 7, 0x00, 48, 48 );
+  TEST_VSETVL( 246, 32, 7, 0x00, 49, 48 );
+  TEST_VSETVL( 247, 32, 7, 0x00, 47, 47 );
 
-  TEST_VSETVL( 248, 32, 8, 0x07, 18, 18 );
-  TEST_VSETVL( 249, 32, 8, 0x07, 19, 18 );
-  TEST_VSETVL( 250, 32, 8, 0x07, 17, 17 );
+  TEST_VSETVL( 248, 32, 8, 0xf8, 18, 18 );
+  TEST_VSETVL( 249, 32, 8, 0xf8, 19, 18 );
+  TEST_VSETVL( 250, 32, 8, 0xf8, 17, 17 );
 
-  TEST_VSETVL( 251, 32, 8, 0xff, 48, 48 );
-  TEST_VSETVL( 252, 32, 8, 0xff, 49, 48 );
-  TEST_VSETVL( 253, 32, 8, 0xff, 47, 47 );
+  TEST_VSETVL( 251, 32, 8, 0x00, 48, 48 );
+  TEST_VSETVL( 252, 32, 8, 0x00, 49, 48 );
+  TEST_VSETVL( 253, 32, 8, 0x00, 47, 47 );
 
-  TEST_VSETVL( 254, 32, 9, 0x07, 18, 18 );
-  TEST_VSETVL( 255, 32, 9, 0x07, 19, 18 );
-  TEST_VSETVL( 256, 32, 9, 0x07, 17, 17 );
+  TEST_VSETVL( 254, 32, 9, 0xf8, 18, 18 );
+  TEST_VSETVL( 255, 32, 9, 0xf8, 19, 18 );
+  TEST_VSETVL( 256, 32, 9, 0xf8, 17, 17 );
 
-  TEST_VSETVL( 257, 32, 9, 0xff, 48, 48 );
-  TEST_VSETVL( 258, 32, 9, 0xff, 49, 48 );
-  TEST_VSETVL( 259, 32, 9, 0xff, 47, 47 );
+  TEST_VSETVL( 257, 32, 9, 0x00, 48, 48 );
+  TEST_VSETVL( 258, 32, 9, 0x00, 49, 48 );
+  TEST_VSETVL( 259, 32, 9, 0x00, 47, 47 );
 
-  TEST_VSETVL( 260, 32, 10, 0x07, 18, 18 );
-  TEST_VSETVL( 261, 32, 10, 0x07, 19, 18 );
-  TEST_VSETVL( 262, 32, 10, 0x07, 17, 17 );
+  TEST_VSETVL( 260, 32, 10, 0xf8, 18, 18 );
+  TEST_VSETVL( 261, 32, 10, 0xf8, 19, 18 );
+  TEST_VSETVL( 262, 32, 10, 0xf8, 17, 17 );
 
-  TEST_VSETVL( 263, 32, 10, 0xff, 48, 48 );
-  TEST_VSETVL( 264, 32, 10, 0xff, 49, 48 );
-  TEST_VSETVL( 265, 32, 10, 0xff, 47, 47 );
+  TEST_VSETVL( 263, 32, 10, 0x00, 48, 48 );
+  TEST_VSETVL( 264, 32, 10, 0x00, 49, 48 );
+  TEST_VSETVL( 265, 32, 10, 0x00, 47, 47 );
 
-  TEST_VSETVL( 266, 32, 11, 0x07, 18, 18 );
-  TEST_VSETVL( 267, 32, 11, 0x07, 19, 18 );
-  TEST_VSETVL( 268, 32, 11, 0x07, 17, 17 );
+  TEST_VSETVL( 266, 32, 11, 0xf8, 18, 18 );
+  TEST_VSETVL( 267, 32, 11, 0xf8, 19, 18 );
+  TEST_VSETVL( 268, 32, 11, 0xf8, 17, 17 );
 
-  TEST_VSETVL( 269, 32, 11, 0xff, 48, 48 );
-  TEST_VSETVL( 270, 32, 11, 0xff, 49, 48 );
-  TEST_VSETVL( 271, 32, 11, 0xff, 47, 47 );
+  TEST_VSETVL( 269, 32, 11, 0x00, 48, 48 );
+  TEST_VSETVL( 270, 32, 11, 0x00, 49, 48 );
+  TEST_VSETVL( 271, 32, 11, 0x00, 47, 47 );
 
-  TEST_VSETVL( 272, 32, 12, 0x07, 15, 15 );
-  TEST_VSETVL( 273, 32, 12, 0x07, 16, 15 );
-  TEST_VSETVL( 274, 32, 12, 0x07, 14, 14 );
+  TEST_VSETVL( 272, 32, 12, 0xf8, 15, 15 );
+  TEST_VSETVL( 273, 32, 12, 0xf8, 16, 15 );
+  TEST_VSETVL( 274, 32, 12, 0xf8, 14, 14 );
 
-  TEST_VSETVL( 275, 32, 12, 0xff, 40, 40 );
-  TEST_VSETVL( 276, 32, 12, 0xff, 41, 40 );
-  TEST_VSETVL( 277, 32, 12, 0xff, 39, 39 );
+  TEST_VSETVL( 275, 32, 12, 0x00, 40, 40 );
+  TEST_VSETVL( 276, 32, 12, 0x00, 41, 40 );
+  TEST_VSETVL( 277, 32, 12, 0x00, 39, 39 );
 
-  TEST_VSETVL( 278, 32, 13, 0x07, 15, 15 );
-  TEST_VSETVL( 279, 32, 13, 0x07, 16, 15 );
-  TEST_VSETVL( 280, 32, 13, 0x07, 14, 14 );
+  TEST_VSETVL( 278, 32, 13, 0xf8, 15, 15 );
+  TEST_VSETVL( 279, 32, 13, 0xf8, 16, 15 );
+  TEST_VSETVL( 280, 32, 13, 0xf8, 14, 14 );
 
-  TEST_VSETVL( 281, 32, 13, 0xff, 40, 40 );
-  TEST_VSETVL( 282, 32, 13, 0xff, 41, 40 );
-  TEST_VSETVL( 283, 32, 13, 0xff, 39, 39 );
+  TEST_VSETVL( 281, 32, 13, 0x00, 40, 40 );
+  TEST_VSETVL( 282, 32, 13, 0x00, 41, 40 );
+  TEST_VSETVL( 283, 32, 13, 0x00, 39, 39 );
 
-  TEST_VSETVL( 284, 32, 14, 0x07, 15, 15 );
-  TEST_VSETVL( 285, 32, 14, 0x07, 16, 15 );
-  TEST_VSETVL( 286, 32, 14, 0x07, 14, 14 );
+  TEST_VSETVL( 284, 32, 14, 0xf8, 15, 15 );
+  TEST_VSETVL( 285, 32, 14, 0xf8, 16, 15 );
+  TEST_VSETVL( 286, 32, 14, 0xf8, 14, 14 );
 
-  TEST_VSETVL( 287, 32, 14, 0xff, 40, 40 );
-  TEST_VSETVL( 288, 32, 14, 0xff, 41, 40 );
-  TEST_VSETVL( 289, 32, 14, 0xff, 39, 39 );
+  TEST_VSETVL( 287, 32, 14, 0x00, 40, 40 );
+  TEST_VSETVL( 288, 32, 14, 0x00, 41, 40 );
+  TEST_VSETVL( 289, 32, 14, 0x00, 39, 39 );
 
-  TEST_VSETVL( 290, 32, 15, 0x07, 15, 15 );
-  TEST_VSETVL( 291, 32, 15, 0x07, 16, 15 );
-  TEST_VSETVL( 292, 32, 15, 0x07, 14, 14 );
+  TEST_VSETVL( 290, 32, 15, 0xf8, 15, 15 );
+  TEST_VSETVL( 291, 32, 15, 0xf8, 16, 15 );
+  TEST_VSETVL( 292, 32, 15, 0xf8, 14, 14 );
 
-  TEST_VSETVL( 293, 32, 15, 0xff, 40, 40 );
-  TEST_VSETVL( 294, 32, 15, 0xff, 41, 40 );
-  TEST_VSETVL( 295, 32, 15, 0xff, 39, 39 );
+  TEST_VSETVL( 293, 32, 15, 0x00, 40, 40 );
+  TEST_VSETVL( 294, 32, 15, 0x00, 41, 40 );
+  TEST_VSETVL( 295, 32, 15, 0x00, 39, 39 );
 
-  TEST_VSETVL( 296, 32, 16, 0x07, 15, 15 );
-  TEST_VSETVL( 297, 32, 16, 0x07, 16, 15 );
-  TEST_VSETVL( 298, 32, 16, 0x07, 14, 14 );
+  TEST_VSETVL( 296, 32, 16, 0xf8, 15, 15 );
+  TEST_VSETVL( 297, 32, 16, 0xf8, 16, 15 );
+  TEST_VSETVL( 298, 32, 16, 0xf8, 14, 14 );
 
-  TEST_VSETVL( 299, 32, 16, 0xff, 40, 40 );
-  TEST_VSETVL( 300, 32, 16, 0xff, 41, 40 );
-  TEST_VSETVL( 301, 32, 16, 0xff, 39, 39 );
+  TEST_VSETVL( 299, 32, 16, 0x00, 40, 40 );
+  TEST_VSETVL( 300, 32, 16, 0x00, 41, 40 );
+  TEST_VSETVL( 301, 32, 16, 0x00, 39, 39 );
 
-  TEST_VSETVL( 302, 32, 17, 0x07, 15, 15 );
-  TEST_VSETVL( 303, 32, 17, 0x07, 16, 15 );
-  TEST_VSETVL( 304, 32, 17, 0x07, 14, 14 );
+  TEST_VSETVL( 302, 32, 17, 0xf8, 15, 15 );
+  TEST_VSETVL( 303, 32, 17, 0xf8, 16, 15 );
+  TEST_VSETVL( 304, 32, 17, 0xf8, 14, 14 );
 
-  TEST_VSETVL( 305, 32, 17, 0xff, 40, 40 );
-  TEST_VSETVL( 306, 32, 17, 0xff, 41, 40 );
-  TEST_VSETVL( 307, 32, 17, 0xff, 39, 39 );
+  TEST_VSETVL( 305, 32, 17, 0x00, 40, 40 );
+  TEST_VSETVL( 306, 32, 17, 0x00, 41, 40 );
+  TEST_VSETVL( 307, 32, 17, 0x00, 39, 39 );
 
-  TEST_VSETVL( 308, 32, 18, 0x07, 15, 15 );
-  TEST_VSETVL( 309, 32, 18, 0x07, 16, 15 );
-  TEST_VSETVL( 310, 32, 18, 0x07, 14, 14 );
+  TEST_VSETVL( 308, 32, 18, 0xf8, 15, 15 );
+  TEST_VSETVL( 309, 32, 18, 0xf8, 16, 15 );
+  TEST_VSETVL( 310, 32, 18, 0xf8, 14, 14 );
 
-  TEST_VSETVL( 311, 32, 18, 0xff, 40, 40 );
-  TEST_VSETVL( 312, 32, 18, 0xff, 41, 40 );
-  TEST_VSETVL( 313, 32, 18, 0xff, 39, 39 );
+  TEST_VSETVL( 311, 32, 18, 0x00, 40, 40 );
+  TEST_VSETVL( 312, 32, 18, 0x00, 41, 40 );
+  TEST_VSETVL( 313, 32, 18, 0x00, 39, 39 );
 
-  TEST_VSETVL( 314, 32, 19, 0x07, 15, 15 );
-  TEST_VSETVL( 315, 32, 19, 0x07, 16, 15 );
-  TEST_VSETVL( 316, 32, 19, 0x07, 14, 14 );
+  TEST_VSETVL( 314, 32, 19, 0xf8, 15, 15 );
+  TEST_VSETVL( 315, 32, 19, 0xf8, 16, 15 );
+  TEST_VSETVL( 316, 32, 19, 0xf8, 14, 14 );
 
-  TEST_VSETVL( 317, 32, 19, 0xff, 40, 40 );
-  TEST_VSETVL( 318, 32, 19, 0xff, 41, 40 );
-  TEST_VSETVL( 319, 32, 19, 0xff, 39, 39 );
+  TEST_VSETVL( 317, 32, 19, 0x00, 40, 40 );
+  TEST_VSETVL( 318, 32, 19, 0x00, 41, 40 );
+  TEST_VSETVL( 319, 32, 19, 0x00, 39, 39 );
 
-  TEST_VSETVL( 320, 32, 20, 0x07, 15, 15 );
-  TEST_VSETVL( 321, 32, 20, 0x07, 16, 15 );
-  TEST_VSETVL( 322, 32, 20, 0x07, 14, 14 );
+  TEST_VSETVL( 320, 32, 20, 0xf8, 15, 15 );
+  TEST_VSETVL( 321, 32, 20, 0xf8, 16, 15 );
+  TEST_VSETVL( 322, 32, 20, 0xf8, 14, 14 );
 
-  TEST_VSETVL( 323, 32, 20, 0xff, 40, 40 );
-  TEST_VSETVL( 324, 32, 20, 0xff, 41, 40 );
-  TEST_VSETVL( 325, 32, 20, 0xff, 39, 39 );
+  TEST_VSETVL( 323, 32, 20, 0x00, 40, 40 );
+  TEST_VSETVL( 324, 32, 20, 0x00, 41, 40 );
+  TEST_VSETVL( 325, 32, 20, 0x00, 39, 39 );
 
-  TEST_VSETVL( 326, 32, 21, 0x07, 12, 12 );
-  TEST_VSETVL( 327, 32, 21, 0x07, 13, 12 );
-  TEST_VSETVL( 328, 32, 21, 0x07, 11, 11 );
+  TEST_VSETVL( 326, 32, 21, 0xf8, 12, 12 );
+  TEST_VSETVL( 327, 32, 21, 0xf8, 13, 12 );
+  TEST_VSETVL( 328, 32, 21, 0xf8, 11, 11 );
 
-  TEST_VSETVL( 329, 32, 21, 0xff, 32, 32 );
-  TEST_VSETVL( 330, 32, 21, 0xff, 33, 32 );
-  TEST_VSETVL( 331, 32, 21, 0xff, 31, 31 );
+  TEST_VSETVL( 329, 32, 21, 0x00, 32, 32 );
+  TEST_VSETVL( 330, 32, 21, 0x00, 33, 32 );
+  TEST_VSETVL( 331, 32, 21, 0x00, 31, 31 );
 
-  TEST_VSETVL( 332, 32, 22, 0x07, 12, 12 );
-  TEST_VSETVL( 333, 32, 22, 0x07, 13, 12 );
-  TEST_VSETVL( 334, 32, 22, 0x07, 11, 11 );
+  TEST_VSETVL( 332, 32, 22, 0xf8, 12, 12 );
+  TEST_VSETVL( 333, 32, 22, 0xf8, 13, 12 );
+  TEST_VSETVL( 334, 32, 22, 0xf8, 11, 11 );
 
-  TEST_VSETVL( 335, 32, 22, 0xff, 32, 32 );
-  TEST_VSETVL( 336, 32, 22, 0xff, 33, 32 );
-  TEST_VSETVL( 337, 32, 22, 0xff, 31, 31 );
+  TEST_VSETVL( 335, 32, 22, 0x00, 32, 32 );
+  TEST_VSETVL( 336, 32, 22, 0x00, 33, 32 );
+  TEST_VSETVL( 337, 32, 22, 0x00, 31, 31 );
 
-  TEST_VSETVL( 338, 32, 23, 0x07, 12, 12 );
-  TEST_VSETVL( 339, 32, 23, 0x07, 13, 12 );
-  TEST_VSETVL( 340, 32, 23, 0x07, 11, 11 );
+  TEST_VSETVL( 338, 32, 23, 0xf8, 12, 12 );
+  TEST_VSETVL( 339, 32, 23, 0xf8, 13, 12 );
+  TEST_VSETVL( 340, 32, 23, 0xf8, 11, 11 );
 
-  TEST_VSETVL( 341, 32, 23, 0xff, 32, 32 );
-  TEST_VSETVL( 342, 32, 23, 0xff, 33, 32 );
-  TEST_VSETVL( 343, 32, 23, 0xff, 31, 31 );
+  TEST_VSETVL( 341, 32, 23, 0x00, 32, 32 );
+  TEST_VSETVL( 342, 32, 23, 0x00, 33, 32 );
+  TEST_VSETVL( 343, 32, 23, 0x00, 31, 31 );
 
-  TEST_VSETVL( 344, 32, 24, 0x07, 12, 12 );
-  TEST_VSETVL( 345, 32, 24, 0x07, 13, 12 );
-  TEST_VSETVL( 346, 32, 24, 0x07, 11, 11 );
+  TEST_VSETVL( 344, 32, 24, 0xf8, 12, 12 );
+  TEST_VSETVL( 345, 32, 24, 0xf8, 13, 12 );
+  TEST_VSETVL( 346, 32, 24, 0xf8, 11, 11 );
 
-  TEST_VSETVL( 347, 32, 24, 0xff, 32, 32 );
-  TEST_VSETVL( 348, 32, 24, 0xff, 33, 32 );
-  TEST_VSETVL( 349, 32, 24, 0xff, 31, 31 );
+  TEST_VSETVL( 347, 32, 24, 0x00, 32, 32 );
+  TEST_VSETVL( 348, 32, 24, 0x00, 33, 32 );
+  TEST_VSETVL( 349, 32, 24, 0x00, 31, 31 );
 
-  TEST_VSETVL( 350, 32, 25, 0x07, 12, 12 );
-  TEST_VSETVL( 351, 32, 25, 0x07, 13, 12 );
-  TEST_VSETVL( 352, 32, 25, 0x07, 11, 11 );
+  TEST_VSETVL( 350, 32, 25, 0xf8, 12, 12 );
+  TEST_VSETVL( 351, 32, 25, 0xf8, 13, 12 );
+  TEST_VSETVL( 352, 32, 25, 0xf8, 11, 11 );
 
-  TEST_VSETVL( 353, 32, 25, 0xff, 32, 32 );
-  TEST_VSETVL( 354, 32, 25, 0xff, 33, 32 );
-  TEST_VSETVL( 355, 32, 25, 0xff, 31, 31 );
+  TEST_VSETVL( 353, 32, 25, 0x00, 32, 32 );
+  TEST_VSETVL( 354, 32, 25, 0x00, 33, 32 );
+  TEST_VSETVL( 355, 32, 25, 0x00, 31, 31 );
 
-  TEST_VSETVL( 356, 32, 26, 0x07, 12, 12 );
-  TEST_VSETVL( 357, 32, 26, 0x07, 13, 12 );
-  TEST_VSETVL( 358, 32, 26, 0x07, 11, 11 );
+  TEST_VSETVL( 356, 32, 26, 0xf8, 12, 12 );
+  TEST_VSETVL( 357, 32, 26, 0xf8, 13, 12 );
+  TEST_VSETVL( 358, 32, 26, 0xf8, 11, 11 );
 
-  TEST_VSETVL( 359, 32, 26, 0xff, 32, 32 );
-  TEST_VSETVL( 360, 32, 26, 0xff, 33, 32 );
-  TEST_VSETVL( 361, 32, 26, 0xff, 31, 31 );
+  TEST_VSETVL( 359, 32, 26, 0x00, 32, 32 );
+  TEST_VSETVL( 360, 32, 26, 0x00, 33, 32 );
+  TEST_VSETVL( 361, 32, 26, 0x00, 31, 31 );
 
-  TEST_VSETVL( 362, 32, 27, 0x07, 12, 12 );
-  TEST_VSETVL( 363, 32, 27, 0x07, 13, 12 );
-  TEST_VSETVL( 364, 32, 27, 0x07, 11, 11 );
+  TEST_VSETVL( 362, 32, 27, 0xf8, 12, 12 );
+  TEST_VSETVL( 363, 32, 27, 0xf8, 13, 12 );
+  TEST_VSETVL( 364, 32, 27, 0xf8, 11, 11 );
 
-  TEST_VSETVL( 365, 32, 27, 0xff, 32, 32 );
-  TEST_VSETVL( 366, 32, 27, 0xff, 33, 32 );
-  TEST_VSETVL( 367, 32, 27, 0xff, 31, 31 );
+  TEST_VSETVL( 365, 32, 27, 0x00, 32, 32 );
+  TEST_VSETVL( 366, 32, 27, 0x00, 33, 32 );
+  TEST_VSETVL( 367, 32, 27, 0x00, 31, 31 );
 
-  TEST_VSETVL( 368, 32, 28, 0x07, 12, 12 );
-  TEST_VSETVL( 369, 32, 28, 0x07, 13, 12 );
-  TEST_VSETVL( 370, 32, 28, 0x07, 11, 11 );
+  TEST_VSETVL( 368, 32, 28, 0xf8, 12, 12 );
+  TEST_VSETVL( 369, 32, 28, 0xf8, 13, 12 );
+  TEST_VSETVL( 370, 32, 28, 0xf8, 11, 11 );
 
-  TEST_VSETVL( 371, 32, 28, 0xff, 32, 32 );
-  TEST_VSETVL( 372, 32, 28, 0xff, 33, 32 );
-  TEST_VSETVL( 373, 32, 28, 0xff, 31, 31 );
+  TEST_VSETVL( 371, 32, 28, 0x00, 32, 32 );
+  TEST_VSETVL( 372, 32, 28, 0x00, 33, 32 );
+  TEST_VSETVL( 373, 32, 28, 0x00, 31, 31 );
 
-  TEST_VSETVL( 374, 32, 29, 0x07, 12, 12 );
-  TEST_VSETVL( 375, 32, 29, 0x07, 13, 12 );
-  TEST_VSETVL( 376, 32, 29, 0x07, 11, 11 );
+  TEST_VSETVL( 374, 32, 29, 0xf8, 12, 12 );
+  TEST_VSETVL( 375, 32, 29, 0xf8, 13, 12 );
+  TEST_VSETVL( 376, 32, 29, 0xf8, 11, 11 );
 
-  TEST_VSETVL( 377, 32, 29, 0xff, 32, 32 );
-  TEST_VSETVL( 378, 32, 29, 0xff, 33, 32 );
-  TEST_VSETVL( 379, 32, 29, 0xff, 31, 31 );
+  TEST_VSETVL( 377, 32, 29, 0x00, 32, 32 );
+  TEST_VSETVL( 378, 32, 29, 0x00, 33, 32 );
+  TEST_VSETVL( 379, 32, 29, 0x00, 31, 31 );
 
-  TEST_VSETVL( 380, 32, 30, 0x07, 12, 12 );
-  TEST_VSETVL( 381, 32, 30, 0x07, 13, 12 );
-  TEST_VSETVL( 382, 32, 30, 0x07, 11, 11 );
+  TEST_VSETVL( 380, 32, 30, 0xf8, 12, 12 );
+  TEST_VSETVL( 381, 32, 30, 0xf8, 13, 12 );
+  TEST_VSETVL( 382, 32, 30, 0xf8, 11, 11 );
 
-  TEST_VSETVL( 383, 32, 30, 0xff, 32, 32 );
-  TEST_VSETVL( 384, 32, 30, 0xff, 33, 32 );
-  TEST_VSETVL( 385, 32, 30, 0xff, 31, 31 );
+  TEST_VSETVL( 383, 32, 30, 0x00, 32, 32 );
+  TEST_VSETVL( 384, 32, 30, 0x00, 33, 32 );
+  TEST_VSETVL( 385, 32, 30, 0x00, 31, 31 );
 
-  TEST_VSETVL( 386, 32, 31, 0x07, 12, 12 );
-  TEST_VSETVL( 387, 32, 31, 0x07, 13, 12 );
-  TEST_VSETVL( 388, 32, 31, 0x07, 11, 11 );
+  TEST_VSETVL( 386, 32, 31, 0xf8, 12, 12 );
+  TEST_VSETVL( 387, 32, 31, 0xf8, 13, 12 );
+  TEST_VSETVL( 388, 32, 31, 0xf8, 11, 11 );
 
-  TEST_VSETVL( 389, 32, 31, 0xff, 32, 32 );
-  TEST_VSETVL( 390, 32, 31, 0xff, 33, 32 );
-  TEST_VSETVL( 391, 32, 31, 0xff, 31, 31 );
+  TEST_VSETVL( 389, 32, 31, 0x00, 32, 32 );
+  TEST_VSETVL( 390, 32, 31, 0x00, 33, 32 );
+  TEST_VSETVL( 391, 32, 31, 0x00, 31, 31 );
 
-  TEST_VSETVL( 392, 32, 32, 0x07, 12, 12 );
-  TEST_VSETVL( 393, 32, 32, 0x07, 13, 12 );
-  TEST_VSETVL( 394, 32, 32, 0x07, 11, 11 );
+  TEST_VSETVL( 392, 32, 32, 0xf8, 12, 12 );
+  TEST_VSETVL( 393, 32, 32, 0xf8, 13, 12 );
+  TEST_VSETVL( 394, 32, 32, 0xf8, 11, 11 );
 
-  TEST_VSETVL( 395, 32, 32, 0xff, 32, 32 );
-  TEST_VSETVL( 396, 32, 32, 0xff, 33, 32 );
-  TEST_VSETVL( 397, 32, 32, 0xff, 31, 31 );
+  TEST_VSETVL( 395, 32, 32, 0x00, 32, 32 );
+  TEST_VSETVL( 396, 32, 32, 0x00, 33, 32 );
+  TEST_VSETVL( 397, 32, 32, 0x00, 31, 31 );
 
   #-------------------------------------------------------------
   # Source/Destination tests

diff --git a/isa/rv64uv/vvadd_branch.S b/isa/rv64uv/vvadd_branch.S
index 191408d57e15ec5fcd099bb23daf1cea3eb457f2..539ba92093c31227dc2f74bb2d0f6dcfcb973e40 100644 (file)
--- a/isa/rv64uv/vvadd_branch.S
+++ b/isa/rv64uv/vvadd_branch.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -22,7 +23,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode1)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,8
@@ -49,7 +50,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx4,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,1
@@ -74,7 +75,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode3)(a0)
   la a5,dest
   vsd vx5,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,4

diff --git a/isa/rv64uv/vvadd_d.S b/isa/rv64uv/vvadd_d.S
index ae9db0319f8b89f8750cc827926fb946495e478d..bf032fa22a5a41dc00c8f27e8f8a0d323c290f4c 100644 (file)
--- a/isa/rv64uv/vvadd_d.S
+++ b/isa/rv64uv/vvadd_d.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -22,7 +23,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode1)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5
@@ -44,7 +45,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx4,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,1
@@ -69,7 +70,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode3)(a0)
   la a5,dest
   vsd vx5,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,4

diff --git a/isa/rv64uv/vvadd_fd.S b/isa/rv64uv/vvadd_fd.S
index bcd417a86c8ba45bf4db25cdde0ea5f0d9ed9a65..7b2ce98ea2e32898d2221b85a7e5ae7685a214d7 100644 (file)
--- a/isa/rv64uv/vvadd_fd.S
+++ b/isa/rv64uv/vvadd_fd.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 32,32
   li a3,4
-  vvcfgivl a3,a3,32,32
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -22,7 +23,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a5,dest
   vfsd vf2,a5
-  fence.v.l
+  fence
   la a5,result
   ld a1,0(a5)
   ld a2,0(a5)

diff --git a/isa/rv64uv/vvadd_fw.S b/isa/rv64uv/vvadd_fw.S
index f857237a0aebfdbb70a42c167b01324136bfee49..0b3138bd3d8fdd4998d2fcb0c22c755087e1521d 100644 (file)
--- a/isa/rv64uv/vvadd_fw.S
+++ b/isa/rv64uv/vvadd_fw.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 32,32
   li a3,4
-  vvcfgivl a3,a3,32,32
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -22,7 +23,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a5,dest
   vfsw vf2,a5
-  fence.v.l
+  fence
   la a6,result
   lw a1,0(a5)
   lw a2,0(a6)

diff --git a/isa/rv64uv/vvadd_w.S b/isa/rv64uv/vvadd_w.S
index f4ad1caf0d3b738a3650874043c08820b8ce37d5..6e194b22fe6ebc8c3616814127e4c8661c3b462d 100644 (file)
--- a/isa/rv64uv/vvadd_w.S
+++ b/isa/rv64uv/vvadd_w.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 32,0
   li a3,9
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -22,7 +23,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a5,dest
   vsw vx2,a5
-  fence.v.l
+  fence
   lw a1,0(a5)
   li a2,10
   li x28,2

diff --git a/isa/rv64uv/vvcfg.S b/isa/rv64uv/vvcfg.S
deleted file mode 100644 (file)
index e474d60..0000000
--- a/isa/rv64uv/vvcfg.S
+++ /dev/null
@@ -1,559 +0,0 @@
-#*****************************************************************************
-# vvcfg.S
-#-----------------------------------------------------------------------------
-#
-# Test vvcfg instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
-  #-------------------------------------------------------------
-  # Arithmetic tests
-  #-------------------------------------------------------------
-
-  TEST_VVCFG( 2, 0, 0, 0x07, 768, 768 );
-  TEST_VVCFG( 3, 0, 0, 0x07, 769, 768 );
-  TEST_VVCFG( 4, 0, 0, 0x07, 767, 767 );
-
-  TEST_VVCFG( 5, 0, 0, 0xff, 2048, 2048 );
-  TEST_VVCFG( 6, 0, 0, 0xff, 2049, 2048 );
-  TEST_VVCFG( 7, 0, 0, 0xff, 2047, 2047 );
-
-  TEST_VVCFG( 8, 1, 0, 0x07, 768, 768 );
-  TEST_VVCFG( 9, 1, 0, 0x07, 769, 768 );
-  TEST_VVCFG( 10, 1, 0, 0x07, 767, 767 );
-
-  TEST_VVCFG( 11, 1, 0, 0xff, 2048, 2048 );
-  TEST_VVCFG( 12, 1, 0, 0xff, 2049, 2048 );
-  TEST_VVCFG( 13, 1, 0, 0xff, 2047, 2047 );
-
-  TEST_VVCFG( 14, 2, 0, 0x07, 768, 768 );
-  TEST_VVCFG( 15, 2, 0, 0x07, 769, 768 );
-  TEST_VVCFG( 16, 2, 0, 0x07, 767, 767 );
-
-  TEST_VVCFG( 17, 2, 0, 0xff, 2048, 2048 );
-  TEST_VVCFG( 18, 2, 0, 0xff, 2049, 2048 );
-  TEST_VVCFG( 19, 2, 0, 0xff, 2047, 2047 );
-
-  TEST_VVCFG( 20, 3, 0, 0x07, 384, 384 );
-  TEST_VVCFG( 21, 3, 0, 0x07, 385, 384 );
-  TEST_VVCFG( 22, 3, 0, 0x07, 383, 383 );
-
-  TEST_VVCFG( 23, 3, 0, 0xff, 1024, 1024 );
-  TEST_VVCFG( 24, 3, 0, 0xff, 1025, 1024 );
-  TEST_VVCFG( 25, 3, 0, 0xff, 1023, 1023 );
-
-  TEST_VVCFG( 26, 4, 0, 0x07, 255, 255 );
-  TEST_VVCFG( 27, 4, 0, 0x07, 256, 255 );
-  TEST_VVCFG( 28, 4, 0, 0x07, 254, 254 );
-
-  TEST_VVCFG( 29, 4, 0, 0xff, 680, 680 );
-  TEST_VVCFG( 30, 4, 0, 0xff, 681, 680 );
-  TEST_VVCFG( 31, 4, 0, 0xff, 679, 679 );
-
-  TEST_VVCFG( 32, 5, 0, 0x07, 192, 192 );
-  TEST_VVCFG( 33, 5, 0, 0x07, 193, 192 );
-  TEST_VVCFG( 34, 5, 0, 0x07, 191, 191 );
-
-  TEST_VVCFG( 35, 5, 0, 0xff, 512, 512 );
-  TEST_VVCFG( 36, 5, 0, 0xff, 513, 512 );
-  TEST_VVCFG( 37, 5, 0, 0xff, 511, 511 );
-
-  TEST_VVCFG( 38, 6, 0, 0x07, 153, 153 );
-  TEST_VVCFG( 39, 6, 0, 0x07, 154, 153 );
-  TEST_VVCFG( 40, 6, 0, 0x07, 152, 152 );
-
-  TEST_VVCFG( 41, 6, 0, 0xff, 408, 408 );
-  TEST_VVCFG( 42, 6, 0, 0xff, 409, 408 );
-  TEST_VVCFG( 43, 6, 0, 0xff, 407, 407 );
-
-  TEST_VVCFG( 44, 7, 0, 0x07, 126, 126 );
-  TEST_VVCFG( 45, 7, 0, 0x07, 127, 126 );
-  TEST_VVCFG( 46, 7, 0, 0x07, 125, 125 );
-
-  TEST_VVCFG( 47, 7, 0, 0xff, 336, 336 );
-  TEST_VVCFG( 48, 7, 0, 0xff, 337, 336 );
-  TEST_VVCFG( 49, 7, 0, 0xff, 335, 335 );
-
-  TEST_VVCFG( 50, 8, 0, 0x07, 108, 108 );
-  TEST_VVCFG( 51, 8, 0, 0x07, 109, 108 );
-  TEST_VVCFG( 52, 8, 0, 0x07, 107, 107 );
-
-  TEST_VVCFG( 53, 8, 0, 0xff, 288, 288 );
-  TEST_VVCFG( 54, 8, 0, 0xff, 289, 288 );
-  TEST_VVCFG( 55, 8, 0, 0xff, 287, 287 );
-
-  TEST_VVCFG( 56, 9, 0, 0x07, 96, 96 );
-  TEST_VVCFG( 57, 9, 0, 0x07, 97, 96 );
-  TEST_VVCFG( 58, 9, 0, 0x07, 95, 95 );
-
-  TEST_VVCFG( 59, 9, 0, 0xff, 256, 256 );
-  TEST_VVCFG( 60, 9, 0, 0xff, 257, 256 );
-  TEST_VVCFG( 61, 9, 0, 0xff, 255, 255 );
-
-  TEST_VVCFG( 62, 10, 0, 0x07, 84, 84 );
-  TEST_VVCFG( 63, 10, 0, 0x07, 85, 84 );
-  TEST_VVCFG( 64, 10, 0, 0x07, 83, 83 );
-
-  TEST_VVCFG( 65, 10, 0, 0xff, 224, 224 );
-  TEST_VVCFG( 66, 10, 0, 0xff, 225, 224 );
-  TEST_VVCFG( 67, 10, 0, 0xff, 223, 223 );
-
-  TEST_VVCFG( 68, 11, 0, 0x07, 75, 75 );
-  TEST_VVCFG( 69, 11, 0, 0x07, 76, 75 );
-  TEST_VVCFG( 70, 11, 0, 0x07, 74, 74 );
-
-  TEST_VVCFG( 71, 11, 0, 0xff, 200, 200 );
-  TEST_VVCFG( 72, 11, 0, 0xff, 201, 200 );
-  TEST_VVCFG( 73, 11, 0, 0xff, 199, 199 );
-
-  TEST_VVCFG( 74, 12, 0, 0x07, 69, 69 );
-  TEST_VVCFG( 75, 12, 0, 0x07, 70, 69 );
-  TEST_VVCFG( 76, 12, 0, 0x07, 68, 68 );
-
-  TEST_VVCFG( 77, 12, 0, 0xff, 184, 184 );
-  TEST_VVCFG( 78, 12, 0, 0xff, 185, 184 );
-  TEST_VVCFG( 79, 12, 0, 0xff, 183, 183 );
-
-  TEST_VVCFG( 80, 13, 0, 0x07, 63, 63 );
-  TEST_VVCFG( 81, 13, 0, 0x07, 64, 63 );
-  TEST_VVCFG( 82, 13, 0, 0x07, 62, 62 );
-
-  TEST_VVCFG( 83, 13, 0, 0xff, 168, 168 );
-  TEST_VVCFG( 84, 13, 0, 0xff, 169, 168 );
-  TEST_VVCFG( 85, 13, 0, 0xff, 167, 167 );
-
-  TEST_VVCFG( 86, 14, 0, 0x07, 57, 57 );
-  TEST_VVCFG( 87, 14, 0, 0x07, 58, 57 );
-  TEST_VVCFG( 88, 14, 0, 0x07, 56, 56 );
-
-  TEST_VVCFG( 89, 14, 0, 0xff, 152, 152 );
-  TEST_VVCFG( 90, 14, 0, 0xff, 153, 152 );
-  TEST_VVCFG( 91, 14, 0, 0xff, 151, 151 );
-
-  TEST_VVCFG( 92, 15, 0, 0x07, 54, 54 );
-  TEST_VVCFG( 93, 15, 0, 0x07, 55, 54 );
-  TEST_VVCFG( 94, 15, 0, 0x07, 53, 53 );
-
-  TEST_VVCFG( 95, 15, 0, 0xff, 144, 144 );
-  TEST_VVCFG( 96, 15, 0, 0xff, 145, 144 );
-  TEST_VVCFG( 97, 15, 0, 0xff, 143, 143 );
-
-  TEST_VVCFG( 98, 16, 0, 0x07, 51, 51 );
-  TEST_VVCFG( 99, 16, 0, 0x07, 52, 51 );
-  TEST_VVCFG( 100, 16, 0, 0x07, 50, 50 );
-
-  TEST_VVCFG( 101, 16, 0, 0xff, 136, 136 );
-  TEST_VVCFG( 102, 16, 0, 0xff, 137, 136 );
-  TEST_VVCFG( 103, 16, 0, 0xff, 135, 135 );
-
-  TEST_VVCFG( 104, 17, 0, 0x07, 48, 48 );
-  TEST_VVCFG( 105, 17, 0, 0x07, 49, 48 );
-  TEST_VVCFG( 106, 17, 0, 0x07, 47, 47 );
-
-  TEST_VVCFG( 107, 17, 0, 0xff, 128, 128 );
-  TEST_VVCFG( 108, 17, 0, 0xff, 129, 128 );
-  TEST_VVCFG( 109, 17, 0, 0xff, 127, 127 );
-
-  TEST_VVCFG( 110, 18, 0, 0x07, 45, 45 );
-  TEST_VVCFG( 111, 18, 0, 0x07, 46, 45 );
-  TEST_VVCFG( 112, 18, 0, 0x07, 44, 44 );
-
-  TEST_VVCFG( 113, 18, 0, 0xff, 120, 120 );
-  TEST_VVCFG( 114, 18, 0, 0xff, 121, 120 );
-  TEST_VVCFG( 115, 18, 0, 0xff, 119, 119 );
-
-  TEST_VVCFG( 116, 19, 0, 0x07, 42, 42 );
-  TEST_VVCFG( 117, 19, 0, 0x07, 43, 42 );
-  TEST_VVCFG( 118, 19, 0, 0x07, 41, 41 );
-
-  TEST_VVCFG( 119, 19, 0, 0xff, 112, 112 );
-  TEST_VVCFG( 120, 19, 0, 0xff, 113, 112 );
-  TEST_VVCFG( 121, 19, 0, 0xff, 111, 111 );
-
-  TEST_VVCFG( 122, 20, 0, 0x07, 39, 39 );
-  TEST_VVCFG( 123, 20, 0, 0x07, 40, 39 );
-  TEST_VVCFG( 124, 20, 0, 0x07, 38, 38 );
-
-  TEST_VVCFG( 125, 20, 0, 0xff, 104, 104 );
-  TEST_VVCFG( 126, 20, 0, 0xff, 105, 104 );
-  TEST_VVCFG( 127, 20, 0, 0xff, 103, 103 );
-
-  TEST_VVCFG( 128, 21, 0, 0x07, 36, 36 );
-  TEST_VVCFG( 129, 21, 0, 0x07, 37, 36 );
-  TEST_VVCFG( 130, 21, 0, 0x07, 35, 35 );
-
-  TEST_VVCFG( 131, 21, 0, 0xff, 96, 96 );
-  TEST_VVCFG( 132, 21, 0, 0xff, 97, 96 );
-  TEST_VVCFG( 133, 21, 0, 0xff, 95, 95 );
-
-  TEST_VVCFG( 134, 22, 0, 0x07, 36, 36 );
-  TEST_VVCFG( 135, 22, 0, 0x07, 37, 36 );
-  TEST_VVCFG( 136, 22, 0, 0x07, 35, 35 );
-
-  TEST_VVCFG( 137, 22, 0, 0xff, 96, 96 );
-  TEST_VVCFG( 138, 22, 0, 0xff, 97, 96 );
-  TEST_VVCFG( 139, 22, 0, 0xff, 95, 95 );
-
-  TEST_VVCFG( 140, 23, 0, 0x07, 33, 33 );
-  TEST_VVCFG( 141, 23, 0, 0x07, 34, 33 );
-  TEST_VVCFG( 142, 23, 0, 0x07, 32, 32 );
-
-  TEST_VVCFG( 143, 23, 0, 0xff, 88, 88 );
-  TEST_VVCFG( 144, 23, 0, 0xff, 89, 88 );
-  TEST_VVCFG( 145, 23, 0, 0xff, 87, 87 );
-
-  TEST_VVCFG( 146, 24, 0, 0x07, 33, 33 );
-  TEST_VVCFG( 147, 24, 0, 0x07, 34, 33 );
-  TEST_VVCFG( 148, 24, 0, 0x07, 32, 32 );
-
-  TEST_VVCFG( 149, 24, 0, 0xff, 88, 88 );
-  TEST_VVCFG( 150, 24, 0, 0xff, 89, 88 );
-  TEST_VVCFG( 151, 24, 0, 0xff, 87, 87 );
-
-  TEST_VVCFG( 152, 25, 0, 0x07, 30, 30 );
-  TEST_VVCFG( 153, 25, 0, 0x07, 31, 30 );
-  TEST_VVCFG( 154, 25, 0, 0x07, 29, 29 );
-
-  TEST_VVCFG( 155, 25, 0, 0xff, 80, 80 );
-  TEST_VVCFG( 156, 25, 0, 0xff, 81, 80 );
-  TEST_VVCFG( 157, 25, 0, 0xff, 79, 79 );
-
-  TEST_VVCFG( 158, 26, 0, 0x07, 30, 30 );
-  TEST_VVCFG( 159, 26, 0, 0x07, 31, 30 );
-  TEST_VVCFG( 160, 26, 0, 0x07, 29, 29 );
-
-  TEST_VVCFG( 161, 26, 0, 0xff, 80, 80 );
-  TEST_VVCFG( 162, 26, 0, 0xff, 81, 80 );
-  TEST_VVCFG( 163, 26, 0, 0xff, 79, 79 );
-
-  TEST_VVCFG( 164, 27, 0, 0x07, 27, 27 );
-  TEST_VVCFG( 165, 27, 0, 0x07, 28, 27 );
-  TEST_VVCFG( 166, 27, 0, 0x07, 26, 26 );
-
-  TEST_VVCFG( 167, 27, 0, 0xff, 72, 72 );
-  TEST_VVCFG( 168, 27, 0, 0xff, 73, 72 );
-  TEST_VVCFG( 169, 27, 0, 0xff, 71, 71 );
-
-  TEST_VVCFG( 170, 28, 0, 0x07, 27, 27 );
-  TEST_VVCFG( 171, 28, 0, 0x07, 28, 27 );
-  TEST_VVCFG( 172, 28, 0, 0x07, 26, 26 );
-
-  TEST_VVCFG( 173, 28, 0, 0xff, 72, 72 );
-  TEST_VVCFG( 174, 28, 0, 0xff, 73, 72 );
-  TEST_VVCFG( 175, 28, 0, 0xff, 71, 71 );
-
-  TEST_VVCFG( 176, 29, 0, 0x07, 27, 27 );
-  TEST_VVCFG( 177, 29, 0, 0x07, 28, 27 );
-  TEST_VVCFG( 178, 29, 0, 0x07, 26, 26 );
-
-  TEST_VVCFG( 179, 29, 0, 0xff, 72, 72 );
-  TEST_VVCFG( 180, 29, 0, 0xff, 73, 72 );
-  TEST_VVCFG( 181, 29, 0, 0xff, 71, 71 );
-
-  TEST_VVCFG( 182, 30, 0, 0x07, 24, 24 );
-  TEST_VVCFG( 183, 30, 0, 0x07, 25, 24 );
-  TEST_VVCFG( 184, 30, 0, 0x07, 23, 23 );
-
-  TEST_VVCFG( 185, 30, 0, 0xff, 64, 64 );
-  TEST_VVCFG( 186, 30, 0, 0xff, 65, 64 );
-  TEST_VVCFG( 187, 30, 0, 0xff, 63, 63 );
-
-  TEST_VVCFG( 188, 31, 0, 0x07, 24, 24 );
-  TEST_VVCFG( 189, 31, 0, 0x07, 25, 24 );
-  TEST_VVCFG( 190, 31, 0, 0x07, 23, 23 );
-
-  TEST_VVCFG( 191, 31, 0, 0xff, 64, 64 );
-  TEST_VVCFG( 192, 31, 0, 0xff, 65, 64 );
-  TEST_VVCFG( 193, 31, 0, 0xff, 63, 63 );
-
-  TEST_VVCFG( 194, 32, 0, 0x07, 24, 24 );
-  TEST_VVCFG( 195, 32, 0, 0x07, 25, 24 );
-  TEST_VVCFG( 196, 32, 0, 0x07, 23, 23 );
-
-  TEST_VVCFG( 197, 32, 0, 0xff, 64, 64 );
-  TEST_VVCFG( 198, 32, 0, 0xff, 65, 64 );
-  TEST_VVCFG( 199, 32, 0, 0xff, 63, 63 );
-
-  TEST_VVCFG( 200, 32, 0, 0x07, 24, 24 );
-  TEST_VVCFG( 201, 32, 0, 0x07, 25, 24 );
-  TEST_VVCFG( 202, 32, 0, 0x07, 23, 23 );
-
-  TEST_VVCFG( 203, 32, 0, 0xff, 64, 64 );
-  TEST_VVCFG( 204, 32, 0, 0xff, 65, 64 );
-  TEST_VVCFG( 205, 32, 0, 0xff, 63, 63 );
-
-  TEST_VVCFG( 206, 32, 1, 0x07, 24, 24 );
-  TEST_VVCFG( 207, 32, 1, 0x07, 25, 24 );
-  TEST_VVCFG( 208, 32, 1, 0x07, 23, 23 );
-
-  TEST_VVCFG( 209, 32, 1, 0xff, 64, 64 );
-  TEST_VVCFG( 210, 32, 1, 0xff, 65, 64 );
-  TEST_VVCFG( 211, 32, 1, 0xff, 63, 63 );
-
-  TEST_VVCFG( 212, 32, 2, 0x07, 21, 21 );
-  TEST_VVCFG( 213, 32, 2, 0x07, 22, 21 );
-  TEST_VVCFG( 214, 32, 2, 0x07, 20, 20 );
-
-  TEST_VVCFG( 215, 32, 2, 0xff, 56, 56 );
-  TEST_VVCFG( 216, 32, 2, 0xff, 57, 56 );
-  TEST_VVCFG( 217, 32, 2, 0xff, 55, 55 );
-
-  TEST_VVCFG( 218, 32, 3, 0x07, 21, 21 );
-  TEST_VVCFG( 219, 32, 3, 0x07, 22, 21 );
-  TEST_VVCFG( 220, 32, 3, 0x07, 20, 20 );
-
-  TEST_VVCFG( 221, 32, 3, 0xff, 56, 56 );
-  TEST_VVCFG( 222, 32, 3, 0xff, 57, 56 );
-  TEST_VVCFG( 223, 32, 3, 0xff, 55, 55 );
-
-  TEST_VVCFG( 224, 32, 4, 0x07, 21, 21 );
-  TEST_VVCFG( 225, 32, 4, 0x07, 22, 21 );
-  TEST_VVCFG( 226, 32, 4, 0x07, 20, 20 );
-
-  TEST_VVCFG( 227, 32, 4, 0xff, 56, 56 );
-  TEST_VVCFG( 228, 32, 4, 0xff, 57, 56 );
-  TEST_VVCFG( 229, 32, 4, 0xff, 55, 55 );
-
-  TEST_VVCFG( 230, 32, 5, 0x07, 21, 21 );
-  TEST_VVCFG( 231, 32, 5, 0x07, 22, 21 );
-  TEST_VVCFG( 232, 32, 5, 0x07, 20, 20 );
-
-  TEST_VVCFG( 233, 32, 5, 0xff, 56, 56 );
-  TEST_VVCFG( 234, 32, 5, 0xff, 57, 56 );
-  TEST_VVCFG( 235, 32, 5, 0xff, 55, 55 );
-
-  TEST_VVCFG( 236, 32, 6, 0x07, 18, 18 );
-  TEST_VVCFG( 237, 32, 6, 0x07, 19, 18 );
-  TEST_VVCFG( 238, 32, 6, 0x07, 17, 17 );
-
-  TEST_VVCFG( 239, 32, 6, 0xff, 48, 48 );
-  TEST_VVCFG( 240, 32, 6, 0xff, 49, 48 );
-  TEST_VVCFG( 241, 32, 6, 0xff, 47, 47 );
-
-  TEST_VVCFG( 242, 32, 7, 0x07, 18, 18 );
-  TEST_VVCFG( 243, 32, 7, 0x07, 19, 18 );
-  TEST_VVCFG( 244, 32, 7, 0x07, 17, 17 );
-
-  TEST_VVCFG( 245, 32, 7, 0xff, 48, 48 );
-  TEST_VVCFG( 246, 32, 7, 0xff, 49, 48 );
-  TEST_VVCFG( 247, 32, 7, 0xff, 47, 47 );
-
-  TEST_VVCFG( 248, 32, 8, 0x07, 18, 18 );
-  TEST_VVCFG( 249, 32, 8, 0x07, 19, 18 );
-  TEST_VVCFG( 250, 32, 8, 0x07, 17, 17 );
-
-  TEST_VVCFG( 251, 32, 8, 0xff, 48, 48 );
-  TEST_VVCFG( 252, 32, 8, 0xff, 49, 48 );
-  TEST_VVCFG( 253, 32, 8, 0xff, 47, 47 );
-
-  TEST_VVCFG( 254, 32, 9, 0x07, 18, 18 );
-  TEST_VVCFG( 255, 32, 9, 0x07, 19, 18 );
-  TEST_VVCFG( 256, 32, 9, 0x07, 17, 17 );
-
-  TEST_VVCFG( 257, 32, 9, 0xff, 48, 48 );
-  TEST_VVCFG( 258, 32, 9, 0xff, 49, 48 );
-  TEST_VVCFG( 259, 32, 9, 0xff, 47, 47 );
-
-  TEST_VVCFG( 260, 32, 10, 0x07, 18, 18 );
-  TEST_VVCFG( 261, 32, 10, 0x07, 19, 18 );
-  TEST_VVCFG( 262, 32, 10, 0x07, 17, 17 );
-
-  TEST_VVCFG( 263, 32, 10, 0xff, 48, 48 );
-  TEST_VVCFG( 264, 32, 10, 0xff, 49, 48 );
-  TEST_VVCFG( 265, 32, 10, 0xff, 47, 47 );
-
-  TEST_VVCFG( 266, 32, 11, 0x07, 18, 18 );
-  TEST_VVCFG( 267, 32, 11, 0x07, 19, 18 );
-  TEST_VVCFG( 268, 32, 11, 0x07, 17, 17 );
-
-  TEST_VVCFG( 269, 32, 11, 0xff, 48, 48 );
-  TEST_VVCFG( 270, 32, 11, 0xff, 49, 48 );
-  TEST_VVCFG( 271, 32, 11, 0xff, 47, 47 );
-
-  TEST_VVCFG( 272, 32, 12, 0x07, 15, 15 );
-  TEST_VVCFG( 273, 32, 12, 0x07, 16, 15 );
-  TEST_VVCFG( 274, 32, 12, 0x07, 14, 14 );
-
-  TEST_VVCFG( 275, 32, 12, 0xff, 40, 40 );
-  TEST_VVCFG( 276, 32, 12, 0xff, 41, 40 );
-  TEST_VVCFG( 277, 32, 12, 0xff, 39, 39 );
-
-  TEST_VVCFG( 278, 32, 13, 0x07, 15, 15 );
-  TEST_VVCFG( 279, 32, 13, 0x07, 16, 15 );
-  TEST_VVCFG( 280, 32, 13, 0x07, 14, 14 );
-
-  TEST_VVCFG( 281, 32, 13, 0xff, 40, 40 );
-  TEST_VVCFG( 282, 32, 13, 0xff, 41, 40 );
-  TEST_VVCFG( 283, 32, 13, 0xff, 39, 39 );
-
-  TEST_VVCFG( 284, 32, 14, 0x07, 15, 15 );
-  TEST_VVCFG( 285, 32, 14, 0x07, 16, 15 );
-  TEST_VVCFG( 286, 32, 14, 0x07, 14, 14 );
-
-  TEST_VVCFG( 287, 32, 14, 0xff, 40, 40 );
-  TEST_VVCFG( 288, 32, 14, 0xff, 41, 40 );
-  TEST_VVCFG( 289, 32, 14, 0xff, 39, 39 );
-
-  TEST_VVCFG( 290, 32, 15, 0x07, 15, 15 );
-  TEST_VVCFG( 291, 32, 15, 0x07, 16, 15 );
-  TEST_VVCFG( 292, 32, 15, 0x07, 14, 14 );
-
-  TEST_VVCFG( 293, 32, 15, 0xff, 40, 40 );
-  TEST_VVCFG( 294, 32, 15, 0xff, 41, 40 );
-  TEST_VVCFG( 295, 32, 15, 0xff, 39, 39 );
-
-  TEST_VVCFG( 296, 32, 16, 0x07, 15, 15 );
-  TEST_VVCFG( 297, 32, 16, 0x07, 16, 15 );
-  TEST_VVCFG( 298, 32, 16, 0x07, 14, 14 );
-
-  TEST_VVCFG( 299, 32, 16, 0xff, 40, 40 );
-  TEST_VVCFG( 300, 32, 16, 0xff, 41, 40 );
-  TEST_VVCFG( 301, 32, 16, 0xff, 39, 39 );
-
-  TEST_VVCFG( 302, 32, 17, 0x07, 15, 15 );
-  TEST_VVCFG( 303, 32, 17, 0x07, 16, 15 );
-  TEST_VVCFG( 304, 32, 17, 0x07, 14, 14 );
-
-  TEST_VVCFG( 305, 32, 17, 0xff, 40, 40 );
-  TEST_VVCFG( 306, 32, 17, 0xff, 41, 40 );
-  TEST_VVCFG( 307, 32, 17, 0xff, 39, 39 );
-
-  TEST_VVCFG( 308, 32, 18, 0x07, 15, 15 );
-  TEST_VVCFG( 309, 32, 18, 0x07, 16, 15 );
-  TEST_VVCFG( 310, 32, 18, 0x07, 14, 14 );
-
-  TEST_VVCFG( 311, 32, 18, 0xff, 40, 40 );
-  TEST_VVCFG( 312, 32, 18, 0xff, 41, 40 );
-  TEST_VVCFG( 313, 32, 18, 0xff, 39, 39 );
-
-  TEST_VVCFG( 314, 32, 19, 0x07, 15, 15 );
-  TEST_VVCFG( 315, 32, 19, 0x07, 16, 15 );
-  TEST_VVCFG( 316, 32, 19, 0x07, 14, 14 );
-
-  TEST_VVCFG( 317, 32, 19, 0xff, 40, 40 );
-  TEST_VVCFG( 318, 32, 19, 0xff, 41, 40 );
-  TEST_VVCFG( 319, 32, 19, 0xff, 39, 39 );
-
-  TEST_VVCFG( 320, 32, 20, 0x07, 15, 15 );
-  TEST_VVCFG( 321, 32, 20, 0x07, 16, 15 );
-  TEST_VVCFG( 322, 32, 20, 0x07, 14, 14 );
-
-  TEST_VVCFG( 323, 32, 20, 0xff, 40, 40 );
-  TEST_VVCFG( 324, 32, 20, 0xff, 41, 40 );
-  TEST_VVCFG( 325, 32, 20, 0xff, 39, 39 );
-
-  TEST_VVCFG( 326, 32, 21, 0x07, 12, 12 );
-  TEST_VVCFG( 327, 32, 21, 0x07, 13, 12 );
-  TEST_VVCFG( 328, 32, 21, 0x07, 11, 11 );
-
-  TEST_VVCFG( 329, 32, 21, 0xff, 32, 32 );
-  TEST_VVCFG( 330, 32, 21, 0xff, 33, 32 );
-  TEST_VVCFG( 331, 32, 21, 0xff, 31, 31 );
-
-  TEST_VVCFG( 332, 32, 22, 0x07, 12, 12 );
-  TEST_VVCFG( 333, 32, 22, 0x07, 13, 12 );
-  TEST_VVCFG( 334, 32, 22, 0x07, 11, 11 );
-
-  TEST_VVCFG( 335, 32, 22, 0xff, 32, 32 );
-  TEST_VVCFG( 336, 32, 22, 0xff, 33, 32 );
-  TEST_VVCFG( 337, 32, 22, 0xff, 31, 31 );
-
-  TEST_VVCFG( 338, 32, 23, 0x07, 12, 12 );
-  TEST_VVCFG( 339, 32, 23, 0x07, 13, 12 );
-  TEST_VVCFG( 340, 32, 23, 0x07, 11, 11 );
-
-  TEST_VVCFG( 341, 32, 23, 0xff, 32, 32 );
-  TEST_VVCFG( 342, 32, 23, 0xff, 33, 32 );
-  TEST_VVCFG( 343, 32, 23, 0xff, 31, 31 );
-
-  TEST_VVCFG( 344, 32, 24, 0x07, 12, 12 );
-  TEST_VVCFG( 345, 32, 24, 0x07, 13, 12 );
-  TEST_VVCFG( 346, 32, 24, 0x07, 11, 11 );
-
-  TEST_VVCFG( 347, 32, 24, 0xff, 32, 32 );
-  TEST_VVCFG( 348, 32, 24, 0xff, 33, 32 );
-  TEST_VVCFG( 349, 32, 24, 0xff, 31, 31 );
-
-  TEST_VVCFG( 350, 32, 25, 0x07, 12, 12 );
-  TEST_VVCFG( 351, 32, 25, 0x07, 13, 12 );
-  TEST_VVCFG( 352, 32, 25, 0x07, 11, 11 );
-
-  TEST_VVCFG( 353, 32, 25, 0xff, 32, 32 );
-  TEST_VVCFG( 354, 32, 25, 0xff, 33, 32 );
-  TEST_VVCFG( 355, 32, 25, 0xff, 31, 31 );
-
-  TEST_VVCFG( 356, 32, 26, 0x07, 12, 12 );
-  TEST_VVCFG( 357, 32, 26, 0x07, 13, 12 );
-  TEST_VVCFG( 358, 32, 26, 0x07, 11, 11 );
-
-  TEST_VVCFG( 359, 32, 26, 0xff, 32, 32 );
-  TEST_VVCFG( 360, 32, 26, 0xff, 33, 32 );
-  TEST_VVCFG( 361, 32, 26, 0xff, 31, 31 );
-
-  TEST_VVCFG( 362, 32, 27, 0x07, 12, 12 );
-  TEST_VVCFG( 363, 32, 27, 0x07, 13, 12 );
-  TEST_VVCFG( 364, 32, 27, 0x07, 11, 11 );
-
-  TEST_VVCFG( 365, 32, 27, 0xff, 32, 32 );
-  TEST_VVCFG( 366, 32, 27, 0xff, 33, 32 );
-  TEST_VVCFG( 367, 32, 27, 0xff, 31, 31 );
-
-  TEST_VVCFG( 368, 32, 28, 0x07, 12, 12 );
-  TEST_VVCFG( 369, 32, 28, 0x07, 13, 12 );
-  TEST_VVCFG( 370, 32, 28, 0x07, 11, 11 );
-
-  TEST_VVCFG( 371, 32, 28, 0xff, 32, 32 );
-  TEST_VVCFG( 372, 32, 28, 0xff, 33, 32 );
-  TEST_VVCFG( 373, 32, 28, 0xff, 31, 31 );
-
-  TEST_VVCFG( 374, 32, 29, 0x07, 12, 12 );
-  TEST_VVCFG( 375, 32, 29, 0x07, 13, 12 );
-  TEST_VVCFG( 376, 32, 29, 0x07, 11, 11 );
-
-  TEST_VVCFG( 377, 32, 29, 0xff, 32, 32 );
-  TEST_VVCFG( 378, 32, 29, 0xff, 33, 32 );
-  TEST_VVCFG( 379, 32, 29, 0xff, 31, 31 );
-
-  TEST_VVCFG( 380, 32, 30, 0x07, 12, 12 );
-  TEST_VVCFG( 381, 32, 30, 0x07, 13, 12 );
-  TEST_VVCFG( 382, 32, 30, 0x07, 11, 11 );
-
-  TEST_VVCFG( 383, 32, 30, 0xff, 32, 32 );
-  TEST_VVCFG( 384, 32, 30, 0xff, 33, 32 );
-  TEST_VVCFG( 385, 32, 30, 0xff, 31, 31 );
-
-  TEST_VVCFG( 386, 32, 31, 0x07, 12, 12 );
-  TEST_VVCFG( 387, 32, 31, 0x07, 13, 12 );
-  TEST_VVCFG( 388, 32, 31, 0x07, 11, 11 );
-
-  TEST_VVCFG( 389, 32, 31, 0xff, 32, 32 );
-  TEST_VVCFG( 390, 32, 31, 0xff, 33, 32 );
-  TEST_VVCFG( 391, 32, 31, 0xff, 31, 31 );
-
-  TEST_VVCFG( 392, 32, 32, 0x07, 12, 12 );
-  TEST_VVCFG( 393, 32, 32, 0x07, 13, 12 );
-  TEST_VVCFG( 394, 32, 32, 0x07, 11, 11 );
-
-  TEST_VVCFG( 395, 32, 32, 0xff, 32, 32 );
-  TEST_VVCFG( 396, 32, 32, 0xff, 33, 32 );
-  TEST_VVCFG( 397, 32, 32, 0xff, 31, 31 );
-
-  #-------------------------------------------------------------
-  # Source/Destination tests
-  #-------------------------------------------------------------
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END

diff --git a/isa/rv64uv/vvcfgivl.S b/isa/rv64uv/vvcfgivl.S
deleted file mode 100644 (file)
index 83e4c1c..0000000
--- a/isa/rv64uv/vvcfgivl.S
+++ /dev/null
@@ -1,559 +0,0 @@
-#*****************************************************************************
-# vvcfgivl.S
-#-----------------------------------------------------------------------------
-#
-# Test vvcfgivl instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
-  #-------------------------------------------------------------
-  # Arithmetic tests
-  #-------------------------------------------------------------
-
-  TEST_VVCFGIVL( 2, 0, 0, 0x07, 768, 768 );
-  TEST_VVCFGIVL( 3, 0, 0, 0x07, 769, 768 );
-  TEST_VVCFGIVL( 4, 0, 0, 0x07, 767, 767 );
-
-  TEST_VVCFGIVL( 5, 0, 0, 0xff, 2048, 2048 );
-  TEST_VVCFGIVL( 6, 0, 0, 0xff, 2049, 2048 );
-  TEST_VVCFGIVL( 7, 0, 0, 0xff, 2047, 2047 );
-
-  TEST_VVCFGIVL( 8, 1, 0, 0x07, 768, 768 );
-  TEST_VVCFGIVL( 9, 1, 0, 0x07, 769, 768 );
-  TEST_VVCFGIVL( 10, 1, 0, 0x07, 767, 767 );
-
-  TEST_VVCFGIVL( 11, 1, 0, 0xff, 2048, 2048 );
-  TEST_VVCFGIVL( 12, 1, 0, 0xff, 2049, 2048 );
-  TEST_VVCFGIVL( 13, 1, 0, 0xff, 2047, 2047 );
-
-  TEST_VVCFGIVL( 14, 2, 0, 0x07, 768, 768 );
-  TEST_VVCFGIVL( 15, 2, 0, 0x07, 769, 768 );
-  TEST_VVCFGIVL( 16, 2, 0, 0x07, 767, 767 );
-
-  TEST_VVCFGIVL( 17, 2, 0, 0xff, 2048, 2048 );
-  TEST_VVCFGIVL( 18, 2, 0, 0xff, 2049, 2048 );
-  TEST_VVCFGIVL( 19, 2, 0, 0xff, 2047, 2047 );
-
-  TEST_VVCFGIVL( 20, 3, 0, 0x07, 384, 384 );
-  TEST_VVCFGIVL( 21, 3, 0, 0x07, 385, 384 );
-  TEST_VVCFGIVL( 22, 3, 0, 0x07, 383, 383 );
-
-  TEST_VVCFGIVL( 23, 3, 0, 0xff, 1024, 1024 );
-  TEST_VVCFGIVL( 24, 3, 0, 0xff, 1025, 1024 );
-  TEST_VVCFGIVL( 25, 3, 0, 0xff, 1023, 1023 );
-
-  TEST_VVCFGIVL( 26, 4, 0, 0x07, 255, 255 );
-  TEST_VVCFGIVL( 27, 4, 0, 0x07, 256, 255 );
-  TEST_VVCFGIVL( 28, 4, 0, 0x07, 254, 254 );
-
-  TEST_VVCFGIVL( 29, 4, 0, 0xff, 680, 680 );
-  TEST_VVCFGIVL( 30, 4, 0, 0xff, 681, 680 );
-  TEST_VVCFGIVL( 31, 4, 0, 0xff, 679, 679 );
-
-  TEST_VVCFGIVL( 32, 5, 0, 0x07, 192, 192 );
-  TEST_VVCFGIVL( 33, 5, 0, 0x07, 193, 192 );
-  TEST_VVCFGIVL( 34, 5, 0, 0x07, 191, 191 );
-
-  TEST_VVCFGIVL( 35, 5, 0, 0xff, 512, 512 );
-  TEST_VVCFGIVL( 36, 5, 0, 0xff, 513, 512 );
-  TEST_VVCFGIVL( 37, 5, 0, 0xff, 511, 511 );
-
-  TEST_VVCFGIVL( 38, 6, 0, 0x07, 153, 153 );
-  TEST_VVCFGIVL( 39, 6, 0, 0x07, 154, 153 );
-  TEST_VVCFGIVL( 40, 6, 0, 0x07, 152, 152 );
-
-  TEST_VVCFGIVL( 41, 6, 0, 0xff, 408, 408 );
-  TEST_VVCFGIVL( 42, 6, 0, 0xff, 409, 408 );
-  TEST_VVCFGIVL( 43, 6, 0, 0xff, 407, 407 );
-
-  TEST_VVCFGIVL( 44, 7, 0, 0x07, 126, 126 );
-  TEST_VVCFGIVL( 45, 7, 0, 0x07, 127, 126 );
-  TEST_VVCFGIVL( 46, 7, 0, 0x07, 125, 125 );
-
-  TEST_VVCFGIVL( 47, 7, 0, 0xff, 336, 336 );
-  TEST_VVCFGIVL( 48, 7, 0, 0xff, 337, 336 );
-  TEST_VVCFGIVL( 49, 7, 0, 0xff, 335, 335 );
-
-  TEST_VVCFGIVL( 50, 8, 0, 0x07, 108, 108 );
-  TEST_VVCFGIVL( 51, 8, 0, 0x07, 109, 108 );
-  TEST_VVCFGIVL( 52, 8, 0, 0x07, 107, 107 );
-
-  TEST_VVCFGIVL( 53, 8, 0, 0xff, 288, 288 );
-  TEST_VVCFGIVL( 54, 8, 0, 0xff, 289, 288 );
-  TEST_VVCFGIVL( 55, 8, 0, 0xff, 287, 287 );
-
-  TEST_VVCFGIVL( 56, 9, 0, 0x07, 96, 96 );
-  TEST_VVCFGIVL( 57, 9, 0, 0x07, 97, 96 );
-  TEST_VVCFGIVL( 58, 9, 0, 0x07, 95, 95 );
-
-  TEST_VVCFGIVL( 59, 9, 0, 0xff, 256, 256 );
-  TEST_VVCFGIVL( 60, 9, 0, 0xff, 257, 256 );
-  TEST_VVCFGIVL( 61, 9, 0, 0xff, 255, 255 );
-
-  TEST_VVCFGIVL( 62, 10, 0, 0x07, 84, 84 );
-  TEST_VVCFGIVL( 63, 10, 0, 0x07, 85, 84 );
-  TEST_VVCFGIVL( 64, 10, 0, 0x07, 83, 83 );
-
-  TEST_VVCFGIVL( 65, 10, 0, 0xff, 224, 224 );
-  TEST_VVCFGIVL( 66, 10, 0, 0xff, 225, 224 );
-  TEST_VVCFGIVL( 67, 10, 0, 0xff, 223, 223 );
-
-  TEST_VVCFGIVL( 68, 11, 0, 0x07, 75, 75 );
-  TEST_VVCFGIVL( 69, 11, 0, 0x07, 76, 75 );
-  TEST_VVCFGIVL( 70, 11, 0, 0x07, 74, 74 );
-
-  TEST_VVCFGIVL( 71, 11, 0, 0xff, 200, 200 );
-  TEST_VVCFGIVL( 72, 11, 0, 0xff, 201, 200 );
-  TEST_VVCFGIVL( 73, 11, 0, 0xff, 199, 199 );
-
-  TEST_VVCFGIVL( 74, 12, 0, 0x07, 69, 69 );
-  TEST_VVCFGIVL( 75, 12, 0, 0x07, 70, 69 );
-  TEST_VVCFGIVL( 76, 12, 0, 0x07, 68, 68 );
-
-  TEST_VVCFGIVL( 77, 12, 0, 0xff, 184, 184 );
-  TEST_VVCFGIVL( 78, 12, 0, 0xff, 185, 184 );
-  TEST_VVCFGIVL( 79, 12, 0, 0xff, 183, 183 );
-
-  TEST_VVCFGIVL( 80, 13, 0, 0x07, 63, 63 );
-  TEST_VVCFGIVL( 81, 13, 0, 0x07, 64, 63 );
-  TEST_VVCFGIVL( 82, 13, 0, 0x07, 62, 62 );
-
-  TEST_VVCFGIVL( 83, 13, 0, 0xff, 168, 168 );
-  TEST_VVCFGIVL( 84, 13, 0, 0xff, 169, 168 );
-  TEST_VVCFGIVL( 85, 13, 0, 0xff, 167, 167 );
-
-  TEST_VVCFGIVL( 86, 14, 0, 0x07, 57, 57 );
-  TEST_VVCFGIVL( 87, 14, 0, 0x07, 58, 57 );
-  TEST_VVCFGIVL( 88, 14, 0, 0x07, 56, 56 );
-
-  TEST_VVCFGIVL( 89, 14, 0, 0xff, 152, 152 );
-  TEST_VVCFGIVL( 90, 14, 0, 0xff, 153, 152 );
-  TEST_VVCFGIVL( 91, 14, 0, 0xff, 151, 151 );
-
-  TEST_VVCFGIVL( 92, 15, 0, 0x07, 54, 54 );
-  TEST_VVCFGIVL( 93, 15, 0, 0x07, 55, 54 );
-  TEST_VVCFGIVL( 94, 15, 0, 0x07, 53, 53 );
-
-  TEST_VVCFGIVL( 95, 15, 0, 0xff, 144, 144 );
-  TEST_VVCFGIVL( 96, 15, 0, 0xff, 145, 144 );
-  TEST_VVCFGIVL( 97, 15, 0, 0xff, 143, 143 );
-
-  TEST_VVCFGIVL( 98, 16, 0, 0x07, 51, 51 );
-  TEST_VVCFGIVL( 99, 16, 0, 0x07, 52, 51 );
-  TEST_VVCFGIVL( 100, 16, 0, 0x07, 50, 50 );
-
-  TEST_VVCFGIVL( 101, 16, 0, 0xff, 136, 136 );
-  TEST_VVCFGIVL( 102, 16, 0, 0xff, 137, 136 );
-  TEST_VVCFGIVL( 103, 16, 0, 0xff, 135, 135 );
-
-  TEST_VVCFGIVL( 104, 17, 0, 0x07, 48, 48 );
-  TEST_VVCFGIVL( 105, 17, 0, 0x07, 49, 48 );
-  TEST_VVCFGIVL( 106, 17, 0, 0x07, 47, 47 );
-
-  TEST_VVCFGIVL( 107, 17, 0, 0xff, 128, 128 );
-  TEST_VVCFGIVL( 108, 17, 0, 0xff, 129, 128 );
-  TEST_VVCFGIVL( 109, 17, 0, 0xff, 127, 127 );
-
-  TEST_VVCFGIVL( 110, 18, 0, 0x07, 45, 45 );
-  TEST_VVCFGIVL( 111, 18, 0, 0x07, 46, 45 );
-  TEST_VVCFGIVL( 112, 18, 0, 0x07, 44, 44 );
-
-  TEST_VVCFGIVL( 113, 18, 0, 0xff, 120, 120 );
-  TEST_VVCFGIVL( 114, 18, 0, 0xff, 121, 120 );
-  TEST_VVCFGIVL( 115, 18, 0, 0xff, 119, 119 );
-
-  TEST_VVCFGIVL( 116, 19, 0, 0x07, 42, 42 );
-  TEST_VVCFGIVL( 117, 19, 0, 0x07, 43, 42 );
-  TEST_VVCFGIVL( 118, 19, 0, 0x07, 41, 41 );
-
-  TEST_VVCFGIVL( 119, 19, 0, 0xff, 112, 112 );
-  TEST_VVCFGIVL( 120, 19, 0, 0xff, 113, 112 );
-  TEST_VVCFGIVL( 121, 19, 0, 0xff, 111, 111 );
-
-  TEST_VVCFGIVL( 122, 20, 0, 0x07, 39, 39 );
-  TEST_VVCFGIVL( 123, 20, 0, 0x07, 40, 39 );
-  TEST_VVCFGIVL( 124, 20, 0, 0x07, 38, 38 );
-
-  TEST_VVCFGIVL( 125, 20, 0, 0xff, 104, 104 );
-  TEST_VVCFGIVL( 126, 20, 0, 0xff, 105, 104 );
-  TEST_VVCFGIVL( 127, 20, 0, 0xff, 103, 103 );
-
-  TEST_VVCFGIVL( 128, 21, 0, 0x07, 36, 36 );
-  TEST_VVCFGIVL( 129, 21, 0, 0x07, 37, 36 );
-  TEST_VVCFGIVL( 130, 21, 0, 0x07, 35, 35 );
-
-  TEST_VVCFGIVL( 131, 21, 0, 0xff, 96, 96 );
-  TEST_VVCFGIVL( 132, 21, 0, 0xff, 97, 96 );
-  TEST_VVCFGIVL( 133, 21, 0, 0xff, 95, 95 );
-
-  TEST_VVCFGIVL( 134, 22, 0, 0x07, 36, 36 );
-  TEST_VVCFGIVL( 135, 22, 0, 0x07, 37, 36 );
-  TEST_VVCFGIVL( 136, 22, 0, 0x07, 35, 35 );
-
-  TEST_VVCFGIVL( 137, 22, 0, 0xff, 96, 96 );
-  TEST_VVCFGIVL( 138, 22, 0, 0xff, 97, 96 );
-  TEST_VVCFGIVL( 139, 22, 0, 0xff, 95, 95 );
-
-  TEST_VVCFGIVL( 140, 23, 0, 0x07, 33, 33 );
-  TEST_VVCFGIVL( 141, 23, 0, 0x07, 34, 33 );
-  TEST_VVCFGIVL( 142, 23, 0, 0x07, 32, 32 );
-
-  TEST_VVCFGIVL( 143, 23, 0, 0xff, 88, 88 );
-  TEST_VVCFGIVL( 144, 23, 0, 0xff, 89, 88 );
-  TEST_VVCFGIVL( 145, 23, 0, 0xff, 87, 87 );
-
-  TEST_VVCFGIVL( 146, 24, 0, 0x07, 33, 33 );
-  TEST_VVCFGIVL( 147, 24, 0, 0x07, 34, 33 );
-  TEST_VVCFGIVL( 148, 24, 0, 0x07, 32, 32 );
-
-  TEST_VVCFGIVL( 149, 24, 0, 0xff, 88, 88 );
-  TEST_VVCFGIVL( 150, 24, 0, 0xff, 89, 88 );
-  TEST_VVCFGIVL( 151, 24, 0, 0xff, 87, 87 );
-
-  TEST_VVCFGIVL( 152, 25, 0, 0x07, 30, 30 );
-  TEST_VVCFGIVL( 153, 25, 0, 0x07, 31, 30 );
-  TEST_VVCFGIVL( 154, 25, 0, 0x07, 29, 29 );
-
-  TEST_VVCFGIVL( 155, 25, 0, 0xff, 80, 80 );
-  TEST_VVCFGIVL( 156, 25, 0, 0xff, 81, 80 );
-  TEST_VVCFGIVL( 157, 25, 0, 0xff, 79, 79 );
-
-  TEST_VVCFGIVL( 158, 26, 0, 0x07, 30, 30 );
-  TEST_VVCFGIVL( 159, 26, 0, 0x07, 31, 30 );
-  TEST_VVCFGIVL( 160, 26, 0, 0x07, 29, 29 );
-
-  TEST_VVCFGIVL( 161, 26, 0, 0xff, 80, 80 );
-  TEST_VVCFGIVL( 162, 26, 0, 0xff, 81, 80 );
-  TEST_VVCFGIVL( 163, 26, 0, 0xff, 79, 79 );
-
-  TEST_VVCFGIVL( 164, 27, 0, 0x07, 27, 27 );
-  TEST_VVCFGIVL( 165, 27, 0, 0x07, 28, 27 );
-  TEST_VVCFGIVL( 166, 27, 0, 0x07, 26, 26 );
-
-  TEST_VVCFGIVL( 167, 27, 0, 0xff, 72, 72 );
-  TEST_VVCFGIVL( 168, 27, 0, 0xff, 73, 72 );
-  TEST_VVCFGIVL( 169, 27, 0, 0xff, 71, 71 );
-
-  TEST_VVCFGIVL( 170, 28, 0, 0x07, 27, 27 );
-  TEST_VVCFGIVL( 171, 28, 0, 0x07, 28, 27 );
-  TEST_VVCFGIVL( 172, 28, 0, 0x07, 26, 26 );
-
-  TEST_VVCFGIVL( 173, 28, 0, 0xff, 72, 72 );
-  TEST_VVCFGIVL( 174, 28, 0, 0xff, 73, 72 );
-  TEST_VVCFGIVL( 175, 28, 0, 0xff, 71, 71 );
-
-  TEST_VVCFGIVL( 176, 29, 0, 0x07, 27, 27 );
-  TEST_VVCFGIVL( 177, 29, 0, 0x07, 28, 27 );
-  TEST_VVCFGIVL( 178, 29, 0, 0x07, 26, 26 );
-
-  TEST_VVCFGIVL( 179, 29, 0, 0xff, 72, 72 );
-  TEST_VVCFGIVL( 180, 29, 0, 0xff, 73, 72 );
-  TEST_VVCFGIVL( 181, 29, 0, 0xff, 71, 71 );
-
-  TEST_VVCFGIVL( 182, 30, 0, 0x07, 24, 24 );
-  TEST_VVCFGIVL( 183, 30, 0, 0x07, 25, 24 );
-  TEST_VVCFGIVL( 184, 30, 0, 0x07, 23, 23 );
-
-  TEST_VVCFGIVL( 185, 30, 0, 0xff, 64, 64 );
-  TEST_VVCFGIVL( 186, 30, 0, 0xff, 65, 64 );
-  TEST_VVCFGIVL( 187, 30, 0, 0xff, 63, 63 );
-
-  TEST_VVCFGIVL( 188, 31, 0, 0x07, 24, 24 );
-  TEST_VVCFGIVL( 189, 31, 0, 0x07, 25, 24 );
-  TEST_VVCFGIVL( 190, 31, 0, 0x07, 23, 23 );
-
-  TEST_VVCFGIVL( 191, 31, 0, 0xff, 64, 64 );
-  TEST_VVCFGIVL( 192, 31, 0, 0xff, 65, 64 );
-  TEST_VVCFGIVL( 193, 31, 0, 0xff, 63, 63 );
-
-  TEST_VVCFGIVL( 194, 32, 0, 0x07, 24, 24 );
-  TEST_VVCFGIVL( 195, 32, 0, 0x07, 25, 24 );
-  TEST_VVCFGIVL( 196, 32, 0, 0x07, 23, 23 );
-
-  TEST_VVCFGIVL( 197, 32, 0, 0xff, 64, 64 );
-  TEST_VVCFGIVL( 198, 32, 0, 0xff, 65, 64 );
-  TEST_VVCFGIVL( 199, 32, 0, 0xff, 63, 63 );
-
-  TEST_VVCFGIVL( 200, 32, 0, 0x07, 24, 24 );
-  TEST_VVCFGIVL( 201, 32, 0, 0x07, 25, 24 );
-  TEST_VVCFGIVL( 202, 32, 0, 0x07, 23, 23 );
-
-  TEST_VVCFGIVL( 203, 32, 0, 0xff, 64, 64 );
-  TEST_VVCFGIVL( 204, 32, 0, 0xff, 65, 64 );
-  TEST_VVCFGIVL( 205, 32, 0, 0xff, 63, 63 );
-
-  TEST_VVCFGIVL( 206, 32, 1, 0x07, 24, 24 );
-  TEST_VVCFGIVL( 207, 32, 1, 0x07, 25, 24 );
-  TEST_VVCFGIVL( 208, 32, 1, 0x07, 23, 23 );
-
-  TEST_VVCFGIVL( 209, 32, 1, 0xff, 64, 64 );
-  TEST_VVCFGIVL( 210, 32, 1, 0xff, 65, 64 );
-  TEST_VVCFGIVL( 211, 32, 1, 0xff, 63, 63 );
-
-  TEST_VVCFGIVL( 212, 32, 2, 0x07, 21, 21 );
-  TEST_VVCFGIVL( 213, 32, 2, 0x07, 22, 21 );
-  TEST_VVCFGIVL( 214, 32, 2, 0x07, 20, 20 );
-
-  TEST_VVCFGIVL( 215, 32, 2, 0xff, 56, 56 );
-  TEST_VVCFGIVL( 216, 32, 2, 0xff, 57, 56 );
-  TEST_VVCFGIVL( 217, 32, 2, 0xff, 55, 55 );
-
-  TEST_VVCFGIVL( 218, 32, 3, 0x07, 21, 21 );
-  TEST_VVCFGIVL( 219, 32, 3, 0x07, 22, 21 );
-  TEST_VVCFGIVL( 220, 32, 3, 0x07, 20, 20 );
-
-  TEST_VVCFGIVL( 221, 32, 3, 0xff, 56, 56 );
-  TEST_VVCFGIVL( 222, 32, 3, 0xff, 57, 56 );
-  TEST_VVCFGIVL( 223, 32, 3, 0xff, 55, 55 );
-
-  TEST_VVCFGIVL( 224, 32, 4, 0x07, 21, 21 );
-  TEST_VVCFGIVL( 225, 32, 4, 0x07, 22, 21 );
-  TEST_VVCFGIVL( 226, 32, 4, 0x07, 20, 20 );
-
-  TEST_VVCFGIVL( 227, 32, 4, 0xff, 56, 56 );
-  TEST_VVCFGIVL( 228, 32, 4, 0xff, 57, 56 );
-  TEST_VVCFGIVL( 229, 32, 4, 0xff, 55, 55 );
-
-  TEST_VVCFGIVL( 230, 32, 5, 0x07, 21, 21 );
-  TEST_VVCFGIVL( 231, 32, 5, 0x07, 22, 21 );
-  TEST_VVCFGIVL( 232, 32, 5, 0x07, 20, 20 );
-
-  TEST_VVCFGIVL( 233, 32, 5, 0xff, 56, 56 );
-  TEST_VVCFGIVL( 234, 32, 5, 0xff, 57, 56 );
-  TEST_VVCFGIVL( 235, 32, 5, 0xff, 55, 55 );
-
-  TEST_VVCFGIVL( 236, 32, 6, 0x07, 18, 18 );
-  TEST_VVCFGIVL( 237, 32, 6, 0x07, 19, 18 );
-  TEST_VVCFGIVL( 238, 32, 6, 0x07, 17, 17 );
-
-  TEST_VVCFGIVL( 239, 32, 6, 0xff, 48, 48 );
-  TEST_VVCFGIVL( 240, 32, 6, 0xff, 49, 48 );
-  TEST_VVCFGIVL( 241, 32, 6, 0xff, 47, 47 );
-
-  TEST_VVCFGIVL( 242, 32, 7, 0x07, 18, 18 );
-  TEST_VVCFGIVL( 243, 32, 7, 0x07, 19, 18 );
-  TEST_VVCFGIVL( 244, 32, 7, 0x07, 17, 17 );
-
-  TEST_VVCFGIVL( 245, 32, 7, 0xff, 48, 48 );
-  TEST_VVCFGIVL( 246, 32, 7, 0xff, 49, 48 );
-  TEST_VVCFGIVL( 247, 32, 7, 0xff, 47, 47 );
-
-  TEST_VVCFGIVL( 248, 32, 8, 0x07, 18, 18 );
-  TEST_VVCFGIVL( 249, 32, 8, 0x07, 19, 18 );
-  TEST_VVCFGIVL( 250, 32, 8, 0x07, 17, 17 );
-
-  TEST_VVCFGIVL( 251, 32, 8, 0xff, 48, 48 );
-  TEST_VVCFGIVL( 252, 32, 8, 0xff, 49, 48 );
-  TEST_VVCFGIVL( 253, 32, 8, 0xff, 47, 47 );
-
-  TEST_VVCFGIVL( 254, 32, 9, 0x07, 18, 18 );
-  TEST_VVCFGIVL( 255, 32, 9, 0x07, 19, 18 );
-  TEST_VVCFGIVL( 256, 32, 9, 0x07, 17, 17 );
-
-  TEST_VVCFGIVL( 257, 32, 9, 0xff, 48, 48 );
-  TEST_VVCFGIVL( 258, 32, 9, 0xff, 49, 48 );
-  TEST_VVCFGIVL( 259, 32, 9, 0xff, 47, 47 );
-
-  TEST_VVCFGIVL( 260, 32, 10, 0x07, 18, 18 );
-  TEST_VVCFGIVL( 261, 32, 10, 0x07, 19, 18 );
-  TEST_VVCFGIVL( 262, 32, 10, 0x07, 17, 17 );
-
-  TEST_VVCFGIVL( 263, 32, 10, 0xff, 48, 48 );
-  TEST_VVCFGIVL( 264, 32, 10, 0xff, 49, 48 );
-  TEST_VVCFGIVL( 265, 32, 10, 0xff, 47, 47 );
-
-  TEST_VVCFGIVL( 266, 32, 11, 0x07, 18, 18 );
-  TEST_VVCFGIVL( 267, 32, 11, 0x07, 19, 18 );
-  TEST_VVCFGIVL( 268, 32, 11, 0x07, 17, 17 );
-
-  TEST_VVCFGIVL( 269, 32, 11, 0xff, 48, 48 );
-  TEST_VVCFGIVL( 270, 32, 11, 0xff, 49, 48 );
-  TEST_VVCFGIVL( 271, 32, 11, 0xff, 47, 47 );
-
-  TEST_VVCFGIVL( 272, 32, 12, 0x07, 15, 15 );
-  TEST_VVCFGIVL( 273, 32, 12, 0x07, 16, 15 );
-  TEST_VVCFGIVL( 274, 32, 12, 0x07, 14, 14 );
-
-  TEST_VVCFGIVL( 275, 32, 12, 0xff, 40, 40 );
-  TEST_VVCFGIVL( 276, 32, 12, 0xff, 41, 40 );
-  TEST_VVCFGIVL( 277, 32, 12, 0xff, 39, 39 );
-
-  TEST_VVCFGIVL( 278, 32, 13, 0x07, 15, 15 );
-  TEST_VVCFGIVL( 279, 32, 13, 0x07, 16, 15 );
-  TEST_VVCFGIVL( 280, 32, 13, 0x07, 14, 14 );
-
-  TEST_VVCFGIVL( 281, 32, 13, 0xff, 40, 40 );
-  TEST_VVCFGIVL( 282, 32, 13, 0xff, 41, 40 );
-  TEST_VVCFGIVL( 283, 32, 13, 0xff, 39, 39 );
-
-  TEST_VVCFGIVL( 284, 32, 14, 0x07, 15, 15 );
-  TEST_VVCFGIVL( 285, 32, 14, 0x07, 16, 15 );
-  TEST_VVCFGIVL( 286, 32, 14, 0x07, 14, 14 );
-
-  TEST_VVCFGIVL( 287, 32, 14, 0xff, 40, 40 );
-  TEST_VVCFGIVL( 288, 32, 14, 0xff, 41, 40 );
-  TEST_VVCFGIVL( 289, 32, 14, 0xff, 39, 39 );
-
-  TEST_VVCFGIVL( 290, 32, 15, 0x07, 15, 15 );
-  TEST_VVCFGIVL( 291, 32, 15, 0x07, 16, 15 );
-  TEST_VVCFGIVL( 292, 32, 15, 0x07, 14, 14 );
-
-  TEST_VVCFGIVL( 293, 32, 15, 0xff, 40, 40 );
-  TEST_VVCFGIVL( 294, 32, 15, 0xff, 41, 40 );
-  TEST_VVCFGIVL( 295, 32, 15, 0xff, 39, 39 );
-
-  TEST_VVCFGIVL( 296, 32, 16, 0x07, 15, 15 );
-  TEST_VVCFGIVL( 297, 32, 16, 0x07, 16, 15 );
-  TEST_VVCFGIVL( 298, 32, 16, 0x07, 14, 14 );
-
-  TEST_VVCFGIVL( 299, 32, 16, 0xff, 40, 40 );
-  TEST_VVCFGIVL( 300, 32, 16, 0xff, 41, 40 );
-  TEST_VVCFGIVL( 301, 32, 16, 0xff, 39, 39 );
-
-  TEST_VVCFGIVL( 302, 32, 17, 0x07, 15, 15 );
-  TEST_VVCFGIVL( 303, 32, 17, 0x07, 16, 15 );
-  TEST_VVCFGIVL( 304, 32, 17, 0x07, 14, 14 );
-
-  TEST_VVCFGIVL( 305, 32, 17, 0xff, 40, 40 );
-  TEST_VVCFGIVL( 306, 32, 17, 0xff, 41, 40 );
-  TEST_VVCFGIVL( 307, 32, 17, 0xff, 39, 39 );
-
-  TEST_VVCFGIVL( 308, 32, 18, 0x07, 15, 15 );
-  TEST_VVCFGIVL( 309, 32, 18, 0x07, 16, 15 );
-  TEST_VVCFGIVL( 310, 32, 18, 0x07, 14, 14 );
-
-  TEST_VVCFGIVL( 311, 32, 18, 0xff, 40, 40 );
-  TEST_VVCFGIVL( 312, 32, 18, 0xff, 41, 40 );
-  TEST_VVCFGIVL( 313, 32, 18, 0xff, 39, 39 );
-
-  TEST_VVCFGIVL( 314, 32, 19, 0x07, 15, 15 );
-  TEST_VVCFGIVL( 315, 32, 19, 0x07, 16, 15 );
-  TEST_VVCFGIVL( 316, 32, 19, 0x07, 14, 14 );
-
-  TEST_VVCFGIVL( 317, 32, 19, 0xff, 40, 40 );
-  TEST_VVCFGIVL( 318, 32, 19, 0xff, 41, 40 );
-  TEST_VVCFGIVL( 319, 32, 19, 0xff, 39, 39 );
-
-  TEST_VVCFGIVL( 320, 32, 20, 0x07, 15, 15 );
-  TEST_VVCFGIVL( 321, 32, 20, 0x07, 16, 15 );
-  TEST_VVCFGIVL( 322, 32, 20, 0x07, 14, 14 );
-
-  TEST_VVCFGIVL( 323, 32, 20, 0xff, 40, 40 );
-  TEST_VVCFGIVL( 324, 32, 20, 0xff, 41, 40 );
-  TEST_VVCFGIVL( 325, 32, 20, 0xff, 39, 39 );
-
-  TEST_VVCFGIVL( 326, 32, 21, 0x07, 12, 12 );
-  TEST_VVCFGIVL( 327, 32, 21, 0x07, 13, 12 );
-  TEST_VVCFGIVL( 328, 32, 21, 0x07, 11, 11 );
-
-  TEST_VVCFGIVL( 329, 32, 21, 0xff, 32, 32 );
-  TEST_VVCFGIVL( 330, 32, 21, 0xff, 33, 32 );
-  TEST_VVCFGIVL( 331, 32, 21, 0xff, 31, 31 );
-
-  TEST_VVCFGIVL( 332, 32, 22, 0x07, 12, 12 );
-  TEST_VVCFGIVL( 333, 32, 22, 0x07, 13, 12 );
-  TEST_VVCFGIVL( 334, 32, 22, 0x07, 11, 11 );
-
-  TEST_VVCFGIVL( 335, 32, 22, 0xff, 32, 32 );
-  TEST_VVCFGIVL( 336, 32, 22, 0xff, 33, 32 );
-  TEST_VVCFGIVL( 337, 32, 22, 0xff, 31, 31 );
-
-  TEST_VVCFGIVL( 338, 32, 23, 0x07, 12, 12 );
-  TEST_VVCFGIVL( 339, 32, 23, 0x07, 13, 12 );
-  TEST_VVCFGIVL( 340, 32, 23, 0x07, 11, 11 );
-
-  TEST_VVCFGIVL( 341, 32, 23, 0xff, 32, 32 );
-  TEST_VVCFGIVL( 342, 32, 23, 0xff, 33, 32 );
-  TEST_VVCFGIVL( 343, 32, 23, 0xff, 31, 31 );
-
-  TEST_VVCFGIVL( 344, 32, 24, 0x07, 12, 12 );
-  TEST_VVCFGIVL( 345, 32, 24, 0x07, 13, 12 );
-  TEST_VVCFGIVL( 346, 32, 24, 0x07, 11, 11 );
-
-  TEST_VVCFGIVL( 347, 32, 24, 0xff, 32, 32 );
-  TEST_VVCFGIVL( 348, 32, 24, 0xff, 33, 32 );
-  TEST_VVCFGIVL( 349, 32, 24, 0xff, 31, 31 );
-
-  TEST_VVCFGIVL( 350, 32, 25, 0x07, 12, 12 );
-  TEST_VVCFGIVL( 351, 32, 25, 0x07, 13, 12 );
-  TEST_VVCFGIVL( 352, 32, 25, 0x07, 11, 11 );
-
-  TEST_VVCFGIVL( 353, 32, 25, 0xff, 32, 32 );
-  TEST_VVCFGIVL( 354, 32, 25, 0xff, 33, 32 );
-  TEST_VVCFGIVL( 355, 32, 25, 0xff, 31, 31 );
-
-  TEST_VVCFGIVL( 356, 32, 26, 0x07, 12, 12 );
-  TEST_VVCFGIVL( 357, 32, 26, 0x07, 13, 12 );
-  TEST_VVCFGIVL( 358, 32, 26, 0x07, 11, 11 );
-
-  TEST_VVCFGIVL( 359, 32, 26, 0xff, 32, 32 );
-  TEST_VVCFGIVL( 360, 32, 26, 0xff, 33, 32 );
-  TEST_VVCFGIVL( 361, 32, 26, 0xff, 31, 31 );
-
-  TEST_VVCFGIVL( 362, 32, 27, 0x07, 12, 12 );
-  TEST_VVCFGIVL( 363, 32, 27, 0x07, 13, 12 );
-  TEST_VVCFGIVL( 364, 32, 27, 0x07, 11, 11 );
-
-  TEST_VVCFGIVL( 365, 32, 27, 0xff, 32, 32 );
-  TEST_VVCFGIVL( 366, 32, 27, 0xff, 33, 32 );
-  TEST_VVCFGIVL( 367, 32, 27, 0xff, 31, 31 );
-
-  TEST_VVCFGIVL( 368, 32, 28, 0x07, 12, 12 );
-  TEST_VVCFGIVL( 369, 32, 28, 0x07, 13, 12 );
-  TEST_VVCFGIVL( 370, 32, 28, 0x07, 11, 11 );
-
-  TEST_VVCFGIVL( 371, 32, 28, 0xff, 32, 32 );
-  TEST_VVCFGIVL( 372, 32, 28, 0xff, 33, 32 );
-  TEST_VVCFGIVL( 373, 32, 28, 0xff, 31, 31 );
-
-  TEST_VVCFGIVL( 374, 32, 29, 0x07, 12, 12 );
-  TEST_VVCFGIVL( 375, 32, 29, 0x07, 13, 12 );
-  TEST_VVCFGIVL( 376, 32, 29, 0x07, 11, 11 );
-
-  TEST_VVCFGIVL( 377, 32, 29, 0xff, 32, 32 );
-  TEST_VVCFGIVL( 378, 32, 29, 0xff, 33, 32 );
-  TEST_VVCFGIVL( 379, 32, 29, 0xff, 31, 31 );
-
-  TEST_VVCFGIVL( 380, 32, 30, 0x07, 12, 12 );
-  TEST_VVCFGIVL( 381, 32, 30, 0x07, 13, 12 );
-  TEST_VVCFGIVL( 382, 32, 30, 0x07, 11, 11 );
-
-  TEST_VVCFGIVL( 383, 32, 30, 0xff, 32, 32 );
-  TEST_VVCFGIVL( 384, 32, 30, 0xff, 33, 32 );
-  TEST_VVCFGIVL( 385, 32, 30, 0xff, 31, 31 );
-
-  TEST_VVCFGIVL( 386, 32, 31, 0x07, 12, 12 );
-  TEST_VVCFGIVL( 387, 32, 31, 0x07, 13, 12 );
-  TEST_VVCFGIVL( 388, 32, 31, 0x07, 11, 11 );
-
-  TEST_VVCFGIVL( 389, 32, 31, 0xff, 32, 32 );
-  TEST_VVCFGIVL( 390, 32, 31, 0xff, 33, 32 );
-  TEST_VVCFGIVL( 391, 32, 31, 0xff, 31, 31 );
-
-  TEST_VVCFGIVL( 392, 32, 32, 0x07, 12, 12 );
-  TEST_VVCFGIVL( 393, 32, 32, 0x07, 13, 12 );
-  TEST_VVCFGIVL( 394, 32, 32, 0x07, 11, 11 );
-
-  TEST_VVCFGIVL( 395, 32, 32, 0xff, 32, 32 );
-  TEST_VVCFGIVL( 396, 32, 32, 0xff, 33, 32 );
-  TEST_VVCFGIVL( 397, 32, 32, 0xff, 31, 31 );
-
-  #-------------------------------------------------------------
-  # Source/Destination tests
-  #-------------------------------------------------------------
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END

diff --git a/isa/rv64uv/vvmul_d.S b/isa/rv64uv/vvmul_d.S
index 9748fa41dd1d44f6cf82b340faea0cb8e060a7b9..335fe3b97c29e22ae1b8bb5e8b2bd22bc63863d5 100644 (file)
--- a/isa/rv64uv/vvmul_d.S
+++ b/isa/rv64uv/vvmul_d.S
@@ -11,8 +11,9 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -22,7 +23,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
   ld a1,0(a5)
   li a2,4
   li x28,2

diff --git a/isa/rv64uv/wakeup.S b/isa/rv64uv/wakeup.S
index 62cc6c8ddfd60fd7fee78466d76356fdbbf04c6a..9fadeba20af3d092b8ce54a09b3a683ce742908b 100644 (file)
--- a/isa/rv64uv/wakeup.S
+++ b/isa/rv64uv/wakeup.S
@@ -12,10 +12,9 @@ RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
   # make sure these don't choke at the beginning
-  fence.v.l
-  fence.v.l
-  fence.v.g
-  fence.v.g
+  fence
+  fence rw,io
+  fence io,rw
 
   # this shouldn't go through since app vl is zero
   la a3,src1
@@ -26,7 +25,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode1)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,0xdeadbeefcafebabe
@@ -61,7 +60,7 @@ RVTEST_CODE_BEGIN
   li x28, 8
   bne a3, a0, fail
 
-  # now do some vector stuff without vvcfgivl
+  # now do some vector stuff without vsetcfg
   vsetvl x0, x0
 
   li a3, 4
@@ -74,7 +73,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode1)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5
@@ -109,7 +108,7 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode1)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,0xdeadbeefcafebabe