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diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index d5f77c376f1ef9e28e79583c3ffdd9fd8a5763b4..19c56d3b4cdb08cb94cce67813760ccdf98fee31 100644 (file)
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -29,22 +29,29 @@ Notes:
 
 # Mask-suited Bitmanipulation
 
+Based on Cray-style masked set-before-first, set-after-first etc.
+and Intel and AMD Bitmanip instructions made generalised then
+advanced further to include masks, this is a single instruction
+covering 24 individual instructions in other ISAs.
+*(sbf/sof/sif moved to [[discussion]])*
+
 BM2-Form
 
     |0     |6    |11    |16    |21-25|26|27..31|
     |------|-----|------|------|-----|--|------|
     | PO   |  RS |   RA |   RB |mode |L |   XO |
 
-
 * bmask RT,RA,RB,mode,L
 
+The patterns within the pseudocode for AMD TBM and x86 BMI1 are
+as follows:
 
-UNDER DEVELOPMENT, sbf/sof/sif moved to [[discussion] and
-general-purpose replacements being designed
+* first pattern A: `x / ~x`
+* second pattern B: `| / & / ^`
+* third pattern C: `x+1 / x-1 / ~(x+1) / -x`
 
-* pattern 1: x / ~x
-* pattern 2: x+1 / x-1 / ~(x+1) / -x
-* pattern 3: | / & / ^
+Thus it makes sense to create a single instruction
+that covers all of these.
 
 Executable pseudocode demo: