gallium/radeon: add separate stencil level dirty flags
authorMarek Olšák <marek.olsak@amd.com>
Sun, 6 Sep 2015 15:35:06 +0000 (17:35 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Sat, 3 Oct 2015 20:06:08 +0000 (22:06 +0200)
We will only do depth-only or stencil-only decompress blits, whichever is
needed by textures, instead of always doing both.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
src/gallium/drivers/r600/evergreen_state.c
src/gallium/drivers/r600/r600_state_common.c
src/gallium/drivers/radeon/r600_pipe_common.h
src/gallium/drivers/radeonsi/cik_sdma.c
src/gallium/drivers/radeonsi/si_dma.c
src/gallium/drivers/radeonsi/si_state_draw.c

index a5caa0dac2ba99e5b1456b34fdc2c0586b18b0c7..6169c5b719befd7bc24142c61589373d38f9f547 100644 (file)
@@ -3375,11 +3375,11 @@ static void evergreen_dma_copy(struct pipe_context *ctx,
        }
 
        if (src->format != dst->format || src_box->depth > 1 ||
-           rdst->dirty_level_mask != 0) {
+           (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level)) {
                goto fallback;
        }
 
-       if (rsrc->dirty_level_mask) {
+       if (rsrc->dirty_level_mask & (1 << src_level)) {
                ctx->flush_resource(ctx, src);
        }
 
index a16f1c25dcbcf518b029d71e6491fbe7878e4e2e..178005a857408e743f890d0279beb4787ed4f17d 100644 (file)
@@ -1779,6 +1779,9 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
                struct r600_texture *rtex = (struct r600_texture *)surf->texture;
 
                rtex->dirty_level_mask |= 1 << surf->u.tex.level;
+
+               if (rtex->surface.flags & RADEON_SURF_SBUFFER)
+                       rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
        }
        if (rctx->framebuffer.compressed_cb_mask) {
                struct pipe_surface *surf;
index 0f9b91af31573d50a52c1bdf44fa219ff2625517..b58b500bd7658a5a4d6a482a656af5cb309bd0f5 100644 (file)
@@ -205,6 +205,7 @@ struct r600_texture {
        unsigned                        pitch_override;
        bool                            is_depth;
        unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
+       unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
        struct r600_texture             *flushed_depth_texture;
        boolean                         is_flushing_texture;
        struct radeon_surf              surface;
index 691d379bccdf7535ce039547f9fdde1cf907bbbf..6454b8ce8c045df9161f67c96eeac65f1a939c9d 100644 (file)
@@ -242,7 +242,7 @@ void cik_sdma_copy(struct pipe_context *ctx,
 
        if (src->format != dst->format ||
            rdst->surface.nsamples > 1 || rsrc->surface.nsamples > 1 ||
-           rdst->dirty_level_mask & (1 << dst_level)) {
+           (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level)) {
                goto fallback;
        }
 
index 3d980fb67b8d7ea909badacfc6bbbb505465c060..31b0b41e5a41c002192834be12bf164422097bd8 100644 (file)
@@ -246,13 +246,13 @@ void si_dma_copy(struct pipe_context *ctx,
        goto fallback;
 
        if (src->format != dst->format || src_box->depth > 1 ||
-           rdst->dirty_level_mask != 0 ||
+           (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level) ||
            rdst->cmask.size || rdst->fmask.size ||
            rsrc->cmask.size || rsrc->fmask.size) {
                goto fallback;
        }
 
-       if (rsrc->dirty_level_mask) {
+       if (rsrc->dirty_level_mask & (1 << src_level)) {
                ctx->flush_resource(ctx, src);
        }
 
index fb65eb3ce2dd7c0a38b3976d77b42a3234b4cacc..43170ec446b96192ad2f3e5bda3474b9a1ac5504 100644 (file)
@@ -858,6 +858,9 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
                struct r600_texture *rtex = (struct r600_texture *)surf->texture;
 
                rtex->dirty_level_mask |= 1 << surf->u.tex.level;
+
+               if (rtex->surface.flags & RADEON_SURF_SBUFFER)
+                       rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
        }
        if (sctx->framebuffer.compressed_cb_mask) {
                struct pipe_surface *surf;