Made obsolete by the libdrm surface allocator.
height = view->base.texture->height0;
depth = view->base.texture->depth0;
- pitch = align(tmp->pitch_in_blocks[0] *
+ pitch = align(tmp->surface.level[0].nblk_x *
util_format_get_blockwidth(tmp->real_format), 8);
array_mode = tmp->array_mode[0];
tile_type = tmp->tile_type;
endian = r600_colorformat_endian_swap(format);
- if (!rscreen->use_surface_alloc) {
- height = texture->height0;
- depth = texture->depth0;
- width = texture->width0;
- pitch = align(tmp->pitch_in_blocks[0] *
- util_format_get_blockwidth(state->format), 8);
- array_mode = tmp->array_mode[0];
- tile_type = tmp->tile_type;
- tile_split = 0;
- macro_aspect = 0;
- bankw = 0;
- bankh = 0;
- } else {
- width = tmp->surface.level[0].npix_x;
- height = tmp->surface.level[0].npix_y;
- depth = tmp->surface.level[0].npix_z;
- pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
- tile_type = tmp->tile_type;
-
- switch (tmp->surface.level[0].mode) {
- case RADEON_SURF_MODE_LINEAR_ALIGNED:
- array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
- break;
- case RADEON_SURF_MODE_2D:
- array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
- break;
- case RADEON_SURF_MODE_1D:
- array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
- break;
- case RADEON_SURF_MODE_LINEAR:
- default:
- array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
- break;
- }
- tile_split = tmp->surface.tile_split;
- macro_aspect = tmp->surface.mtilea;
- bankw = tmp->surface.bankw;
- bankh = tmp->surface.bankh;
- tile_split = eg_tile_split(tile_split);
- macro_aspect = eg_macro_tile_aspect(macro_aspect);
- bankw = eg_bank_wh(bankw);
- bankh = eg_bank_wh(bankh);
+ width = tmp->surface.level[0].npix_x;
+ height = tmp->surface.level[0].npix_y;
+ depth = tmp->surface.level[0].npix_z;
+ pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
+ tile_type = tmp->tile_type;
+
+ switch (tmp->surface.level[0].mode) {
+ case RADEON_SURF_MODE_LINEAR_ALIGNED:
+ array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
+ break;
+ case RADEON_SURF_MODE_2D:
+ array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
+ break;
+ case RADEON_SURF_MODE_1D:
+ array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
+ break;
+ case RADEON_SURF_MODE_LINEAR:
+ default:
+ array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
+ break;
}
+ tile_split = tmp->surface.tile_split;
+ macro_aspect = tmp->surface.mtilea;
+ bankw = tmp->surface.bankw;
+ bankh = tmp->surface.bankh;
+ tile_split = eg_tile_split(tile_split);
+ macro_aspect = eg_macro_tile_aspect(macro_aspect);
+ bankw = eg_bank_wh(bankw);
+ bankh = eg_bank_wh(bankh);
+
/* 128 bit formats require tile type = 1 */
if (rscreen->chip_class == CAYMAN) {
if (util_format_get_blocksize(state->format) >= 16)
assert(rtex);
}
- /* XXX quite sure for dx10+ hw don't need any offset hacks */
- if (!rscreen->use_surface_alloc) {
- offset = r600_texture_get_offset(rtex,
- level, state->cbufs[cb]->u.tex.first_layer);
- pitch = rtex->pitch_in_blocks[level] / 8 - 1;
- slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
- if (slice) {
- slice = slice - 1;
- }
- color_info = S_028C70_ARRAY_MODE(rtex->array_mode[level]);
- tile_split = 0;
- macro_aspect = 0;
- bankw = 0;
- bankh = 0;
- if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
- tile_type = rtex->tile_type;
- } else {
- /* workaround for linear buffers */
- tile_type = 1;
- }
- } else {
- offset = rtex->surface.level[level].offset;
- if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
- offset += rtex->surface.level[level].slice_size *
- state->cbufs[cb]->u.tex.first_layer;
- }
- pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
- slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
- if (slice) {
- slice = slice - 1;
- }
- color_info = 0;
- switch (rtex->surface.level[level].mode) {
- case RADEON_SURF_MODE_LINEAR_ALIGNED:
- color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
- tile_type = 1;
- break;
- case RADEON_SURF_MODE_1D:
- color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
- tile_type = rtex->tile_type;
- break;
- case RADEON_SURF_MODE_2D:
- color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
- tile_type = rtex->tile_type;
- break;
- case RADEON_SURF_MODE_LINEAR:
- default:
- color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
- tile_type = 1;
- break;
- }
- tile_split = rtex->surface.tile_split;
- macro_aspect = rtex->surface.mtilea;
- bankw = rtex->surface.bankw;
- bankh = rtex->surface.bankh;
- tile_split = eg_tile_split(tile_split);
- macro_aspect = eg_macro_tile_aspect(macro_aspect);
- bankw = eg_bank_wh(bankw);
- bankh = eg_bank_wh(bankh);
+ offset = rtex->surface.level[level].offset;
+ if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
+ offset += rtex->surface.level[level].slice_size *
+ state->cbufs[cb]->u.tex.first_layer;
+ }
+ pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
+ slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
+ if (slice) {
+ slice = slice - 1;
}
+ color_info = 0;
+ switch (rtex->surface.level[level].mode) {
+ case RADEON_SURF_MODE_LINEAR_ALIGNED:
+ color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
+ tile_type = 1;
+ break;
+ case RADEON_SURF_MODE_1D:
+ color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
+ tile_type = rtex->tile_type;
+ break;
+ case RADEON_SURF_MODE_2D:
+ color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
+ tile_type = rtex->tile_type;
+ break;
+ case RADEON_SURF_MODE_LINEAR:
+ default:
+ color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
+ tile_type = 1;
+ break;
+ }
+ tile_split = rtex->surface.tile_split;
+ macro_aspect = rtex->surface.mtilea;
+ bankw = rtex->surface.bankw;
+ bankh = rtex->surface.bankh;
+ tile_split = eg_tile_split(tile_split);
+ macro_aspect = eg_macro_tile_aspect(macro_aspect);
+ bankw = eg_bank_wh(bankw);
+ bankh = eg_bank_wh(bankh);
+
/* 128 bit formats require tile type = 1 */
if (rscreen->chip_class == CAYMAN) {
if (util_format_get_blocksize(surf->base.format) >= 16)
r600_pipe_state_add_reg(rstate,
R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
S_028C68_SLICE_TILE_MAX(slice));
- if (!rscreen->use_surface_alloc) {
+ if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
r600_pipe_state_add_reg(rstate,
R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
0x00000000);
} else {
- if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
- r600_pipe_state_add_reg(rstate,
- R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
- 0x00000000);
- } else {
- r600_pipe_state_add_reg(rstate,
- R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
- S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
- S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
- }
+ r600_pipe_state_add_reg(rstate,
+ R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
+ S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
+ S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
}
r600_pipe_state_add_reg_bo(rstate,
R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
struct r600_resource_texture *rtex;
struct r600_surface *surf;
uint64_t offset;
- unsigned level, first_layer, pitch, slice, format, array_mode;
+ unsigned level, pitch, slice, format, array_mode;
unsigned macro_aspect, tile_split, bankh, bankw, z_info, nbanks;
if (state->zsbuf == NULL)
surf = (struct r600_surface *)state->zsbuf;
level = surf->base.u.tex.level;
rtex = (struct r600_resource_texture*)surf->base.texture;
- first_layer = surf->base.u.tex.first_layer;
format = r600_translate_dbformat(surf->base.format);
assert(format != ~0);
offset = r600_resource_va(rctx->context.screen, surf->base.texture);
- /* XXX remove this once tiling is properly supported */
- if (!rscreen->use_surface_alloc) {
- /* XXX remove this once tiling is properly supported */
- array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
- V_028C70_ARRAY_1D_TILED_THIN1;
-
- offset += r600_texture_get_offset(rtex, level, first_layer);
- pitch = (rtex->pitch_in_blocks[level] / 8) - 1;
- slice = ((rtex->pitch_in_blocks[level] * surf->aligned_height) / 64);
- if (slice) {
- slice = slice - 1;
- }
- tile_split = 0;
- macro_aspect = 0;
- bankw = 0;
- bankh = 0;
- } else {
- offset += rtex->surface.level[level].offset;
- pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
- slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
- if (slice) {
- slice = slice - 1;
- }
- switch (rtex->surface.level[level].mode) {
- case RADEON_SURF_MODE_2D:
- array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
- break;
- case RADEON_SURF_MODE_1D:
- case RADEON_SURF_MODE_LINEAR_ALIGNED:
- case RADEON_SURF_MODE_LINEAR:
- default:
- array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
- break;
- }
- tile_split = rtex->surface.tile_split;
- macro_aspect = rtex->surface.mtilea;
- bankw = rtex->surface.bankw;
- bankh = rtex->surface.bankh;
- tile_split = eg_tile_split(tile_split);
- macro_aspect = eg_macro_tile_aspect(macro_aspect);
- bankw = eg_bank_wh(bankw);
- bankh = eg_bank_wh(bankh);
+ offset += rtex->surface.level[level].offset;
+ pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
+ slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
+ if (slice) {
+ slice = slice - 1;
+ }
+ switch (rtex->surface.level[level].mode) {
+ case RADEON_SURF_MODE_2D:
+ array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
+ break;
+ case RADEON_SURF_MODE_1D:
+ case RADEON_SURF_MODE_LINEAR_ALIGNED:
+ case RADEON_SURF_MODE_LINEAR:
+ default:
+ array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
+ break;
}
+ tile_split = rtex->surface.tile_split;
+ macro_aspect = rtex->surface.mtilea;
+ bankw = rtex->surface.bankw;
+ bankh = rtex->surface.bankh;
+ tile_split = eg_tile_split(tile_split);
+ macro_aspect = eg_macro_tile_aspect(macro_aspect);
+ bankw = eg_bank_wh(bankw);
+ bankh = eg_bank_wh(bankh);
nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
offset >>= 8;
offset, &rtex->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE,
offset, &rtex->resource, RADEON_USAGE_READWRITE);
- if (!rscreen->use_surface_alloc) {
- r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
- 0x00000000);
- } else {
- r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
- S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
- S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
- }
+ r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
+ S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
+ S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
- if (rtex->stencil) {
- uint64_t stencil_offset =
- r600_texture_get_offset(rtex->stencil, level, first_layer);
- unsigned stile_split;
+ if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+ uint64_t stencil_offset = rtex->surface.stencil_offset;
+ unsigned stile_split = rtex->surface.stencil_tile_split;
- stile_split = eg_tile_split(rtex->stencil->surface.tile_split);
- stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
+ stile_split = eg_tile_split(stile_split);
+ stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
+ stencil_offset += rtex->surface.level[level].offset / 4;
stencil_offset >>= 8;
r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
- stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
+ stencil_offset, &rtex->resource,
+ RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
- stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
+ stencil_offset, &rtex->resource,
+ RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1 | S_028044_TILE_SPLIT(stile_split),
- &rtex->stencil->resource, RADEON_USAGE_READWRITE);
+ &rtex->resource,
+ RADEON_USAGE_READWRITE);
} else {
- if (rscreen->use_surface_alloc && rtex->surface.flags & RADEON_SURF_SBUFFER) {
- uint64_t stencil_offset = rtex->surface.stencil_offset;
- unsigned stile_split = rtex->surface.stencil_tile_split;
-
- stile_split = eg_tile_split(stile_split);
- stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
- stencil_offset += rtex->surface.level[level].offset / 4;
- stencil_offset >>= 8;
-
- r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
- stencil_offset, &rtex->resource,
- RADEON_USAGE_READWRITE);
- r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
- stencil_offset, &rtex->resource,
- RADEON_USAGE_READWRITE);
- r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
- 1 | S_028044_TILE_SPLIT(stile_split),
- &rtex->resource,
- RADEON_USAGE_READWRITE);
- } else {
- r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
- offset, &rtex->resource,
- RADEON_USAGE_READWRITE);
- r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
- offset, &rtex->resource,
- RADEON_USAGE_READWRITE);
- r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
- 1, NULL, RADEON_USAGE_READWRITE);
- }
+ r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
+ offset, &rtex->resource,
+ RADEON_USAGE_READWRITE);
+ r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
+ offset, &rtex->resource,
+ RADEON_USAGE_READWRITE);
+ r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
+ 1, NULL, RADEON_USAGE_READWRITE);
}
r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, z_info,
LIST_INITHEAD(&rscreen->fences.blocks);
pipe_mutex_init(rscreen->fences.mutex);
- rscreen->use_surface_alloc = debug_get_bool_option("R600_SURF", TRUE);
-
rscreen->global_pool = compute_memory_pool_new(rscreen);
return &rscreen->screen;
struct r600_tiling_info tiling_info;
struct r600_pipe_fences fences;
- bool use_surface_alloc;
-
/*for compute global memory binding, we allocate stuff here, instead of
* buffers.
* XXX: Not sure if this is the best place for global_pool. Also,
unsigned offset[PIPE_MAX_TEXTURE_LEVELS];
unsigned pitch_in_bytes[PIPE_MAX_TEXTURE_LEVELS]; /* transfer */
- unsigned pitch_in_blocks[PIPE_MAX_TEXTURE_LEVELS]; /* texture resource */
unsigned layer_size[PIPE_MAX_TEXTURE_LEVELS];
unsigned array_mode[PIPE_MAX_TEXTURE_LEVELS];
unsigned pitch_override;
bool is_depth;
bool is_rat;
unsigned dirty_db_mask; /* each bit says if that miplevel is dirty */
- struct r600_resource_texture *stencil; /* Stencil is in a separate buffer on Evergreen. */
struct r600_resource_texture *flushed_depth_texture;
boolean is_flushing_texture;
struct radeon_surface surface;
struct r600_surface {
struct pipe_surface base;
- unsigned aligned_height;
};
void r600_resource_destroy(struct pipe_screen *screen, struct pipe_resource *res);
struct pipe_resource *texture,
const struct pipe_sampler_view *state)
{
- struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
unsigned format, endian;
offset_level = state->u.tex.first_level;
last_level = state->u.tex.last_level - offset_level;
- if (!rscreen->use_surface_alloc) {
- width = u_minify(texture->width0, offset_level);
- height = u_minify(texture->height0, offset_level);
- depth = u_minify(texture->depth0, offset_level);
-
- pitch = align(tmp->pitch_in_blocks[offset_level] *
- util_format_get_blockwidth(state->format), 8);
- array_mode = tmp->array_mode[offset_level];
- tile_type = tmp->tile_type;
-
- if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
- height = 1;
- depth = texture->array_size;
- } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
- depth = texture->array_size;
- }
+ width = tmp->surface.level[offset_level].npix_x;
+ height = tmp->surface.level[offset_level].npix_y;
+ depth = tmp->surface.level[offset_level].npix_z;
+ pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
+ tile_type = tmp->tile_type;
+
+ if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
+ height = 1;
+ depth = texture->array_size;
+ } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
+ depth = texture->array_size;
+ }
+ switch (tmp->surface.level[offset_level].mode) {
+ case RADEON_SURF_MODE_LINEAR_ALIGNED:
+ array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
+ break;
+ case RADEON_SURF_MODE_1D:
+ array_mode = V_038000_ARRAY_1D_TILED_THIN1;
+ break;
+ case RADEON_SURF_MODE_2D:
+ array_mode = V_038000_ARRAY_2D_TILED_THIN1;
+ break;
+ case RADEON_SURF_MODE_LINEAR:
+ default:
+ array_mode = V_038000_ARRAY_LINEAR_GENERAL;
+ break;
+ }
- view->tex_resource = &tmp->resource;
- view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
- S_038000_TILE_MODE(array_mode) |
- S_038000_TILE_TYPE(tile_type) |
- S_038000_PITCH((pitch / 8) - 1) |
- S_038000_TEX_WIDTH(width - 1));
- view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
- S_038004_TEX_DEPTH(depth - 1) |
- S_038004_DATA_FORMAT(format));
- view->tex_resource_words[2] = tmp->offset[offset_level] >> 8;
- view->tex_resource_words[3] = tmp->offset[offset_level+1] >> 8;
- view->tex_resource_words[4] = (word4 |
- S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
- S_038010_REQUEST_SIZE(1) |
- S_038010_ENDIAN_SWAP(endian) |
- S_038010_BASE_LEVEL(0));
- view->tex_resource_words[5] = (S_038014_LAST_LEVEL(last_level) |
- S_038014_BASE_ARRAY(state->u.tex.first_layer) |
- S_038014_LAST_ARRAY(state->u.tex.last_layer));
- view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
- S_038018_MAX_ANISO(4 /* max 16 samples */));
+ view->tex_resource = &tmp->resource;
+ view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
+ S_038000_TILE_MODE(array_mode) |
+ S_038000_TILE_TYPE(tile_type) |
+ S_038000_PITCH((pitch / 8) - 1) |
+ S_038000_TEX_WIDTH(width - 1));
+ view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
+ S_038004_TEX_DEPTH(depth - 1) |
+ S_038004_DATA_FORMAT(format));
+ view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
+ if (offset_level >= tmp->surface.last_level) {
+ view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
} else {
- width = tmp->surface.level[offset_level].npix_x;
- height = tmp->surface.level[offset_level].npix_y;
- depth = tmp->surface.level[offset_level].npix_z;
- pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
- tile_type = tmp->tile_type;
-
- if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
- height = 1;
- depth = texture->array_size;
- } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
- depth = texture->array_size;
- }
- switch (tmp->surface.level[offset_level].mode) {
- case RADEON_SURF_MODE_LINEAR_ALIGNED:
- array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
- break;
- case RADEON_SURF_MODE_1D:
- array_mode = V_038000_ARRAY_1D_TILED_THIN1;
- break;
- case RADEON_SURF_MODE_2D:
- array_mode = V_038000_ARRAY_2D_TILED_THIN1;
- break;
- case RADEON_SURF_MODE_LINEAR:
- default:
- array_mode = V_038000_ARRAY_LINEAR_GENERAL;
- break;
- }
-
- view->tex_resource = &tmp->resource;
- view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
- S_038000_TILE_MODE(array_mode) |
- S_038000_TILE_TYPE(tile_type) |
- S_038000_PITCH((pitch / 8) - 1) |
- S_038000_TEX_WIDTH(width - 1));
- view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
- S_038004_TEX_DEPTH(depth - 1) |
- S_038004_DATA_FORMAT(format));
- view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
- if (offset_level >= tmp->surface.last_level) {
- view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
- } else {
- view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
- }
- view->tex_resource_words[4] = (word4 |
- S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
- S_038010_REQUEST_SIZE(1) |
- S_038010_ENDIAN_SWAP(endian) |
- S_038010_BASE_LEVEL(0));
- view->tex_resource_words[5] = (S_038014_LAST_LEVEL(last_level) |
- S_038014_BASE_ARRAY(state->u.tex.first_layer) |
- S_038014_LAST_ARRAY(state->u.tex.last_layer));
- view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
- S_038018_MAX_ANISO(4 /* max 16 samples */));
- }
+ view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
+ }
+ view->tex_resource_words[4] = (word4 |
+ S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
+ S_038010_REQUEST_SIZE(1) |
+ S_038010_ENDIAN_SWAP(endian) |
+ S_038010_BASE_LEVEL(0));
+ view->tex_resource_words[5] = (S_038014_LAST_LEVEL(last_level) |
+ S_038014_BASE_ARRAY(state->u.tex.first_layer) |
+ S_038014_LAST_ARRAY(state->u.tex.last_layer));
+ view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
+ S_038018_MAX_ANISO(4 /* max 16 samples */));
return &view->base;
}
static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
const struct pipe_framebuffer_state *state, int cb)
{
- struct r600_screen *rscreen = rctx->screen;
struct r600_resource_texture *rtex;
struct r600_surface *surf;
unsigned level = state->cbufs[cb]->u.tex.level;
rtex = rtex->flushed_depth_texture;
}
- /* XXX quite sure for dx10+ hw don't need any offset hacks */
- if (!rscreen->use_surface_alloc) {
- offset = r600_texture_get_offset(rtex,
- level, state->cbufs[cb]->u.tex.first_layer);
- pitch = rtex->pitch_in_blocks[level] / 8 - 1;
- slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
- if (slice) {
- slice = slice - 1;
- }
- color_info = S_0280A0_ARRAY_MODE(rtex->array_mode[level]);
- } else {
- offset = rtex->surface.level[level].offset;
- if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
- offset += rtex->surface.level[level].slice_size *
- state->cbufs[cb]->u.tex.first_layer;
- }
- pitch = rtex->surface.level[level].nblk_x / 8 - 1;
- slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
- if (slice) {
- slice = slice - 1;
- }
- color_info = 0;
- switch (rtex->surface.level[level].mode) {
- case RADEON_SURF_MODE_LINEAR_ALIGNED:
- color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
- break;
- case RADEON_SURF_MODE_1D:
- color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
- break;
- case RADEON_SURF_MODE_2D:
- color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
- break;
- case RADEON_SURF_MODE_LINEAR:
- default:
- color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
- break;
- }
+ offset = rtex->surface.level[level].offset;
+ if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
+ offset += rtex->surface.level[level].slice_size *
+ state->cbufs[cb]->u.tex.first_layer;
+ }
+ pitch = rtex->surface.level[level].nblk_x / 8 - 1;
+ slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
+ if (slice) {
+ slice = slice - 1;
+ }
+ color_info = 0;
+ switch (rtex->surface.level[level].mode) {
+ case RADEON_SURF_MODE_LINEAR_ALIGNED:
+ color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
+ break;
+ case RADEON_SURF_MODE_1D:
+ color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
+ break;
+ case RADEON_SURF_MODE_2D:
+ color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
+ break;
+ case RADEON_SURF_MODE_LINEAR:
+ default:
+ color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
+ break;
}
+
desc = util_format_description(surf->base.format);
for (i = 0; i < 4; i++) {
R_028060_CB_COLOR0_SIZE + cb * 4,
S_028060_PITCH_TILE_MAX(pitch) |
S_028060_SLICE_TILE_MAX(slice));
- if (!rscreen->use_surface_alloc) {
+ if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
r600_pipe_state_add_reg(rstate,
R_028080_CB_COLOR0_VIEW + cb * 4,
0x00000000);
} else {
- if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
- r600_pipe_state_add_reg(rstate,
- R_028080_CB_COLOR0_VIEW + cb * 4,
- 0x00000000);
- } else {
- r600_pipe_state_add_reg(rstate,
- R_028080_CB_COLOR0_VIEW + cb * 4,
- S_028080_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
- S_028080_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
- }
+ r600_pipe_state_add_reg(rstate,
+ R_028080_CB_COLOR0_VIEW + cb * 4,
+ S_028080_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
+ S_028080_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
}
r600_pipe_state_add_reg_bo(rstate,
R_0280E0_CB_COLOR0_FRAG + cb * 4,
static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
const struct pipe_framebuffer_state *state)
{
- struct r600_screen *rscreen = rctx->screen;
struct r600_resource_texture *rtex;
- struct r600_surface *surf;
unsigned level, pitch, slice, format, offset, array_mode;
if (state->zsbuf == NULL)
level = state->zsbuf->u.tex.level;
- surf = (struct r600_surface *)state->zsbuf;
rtex = (struct r600_resource_texture*)state->zsbuf->texture;
- if (!rscreen->use_surface_alloc) {
- /* XXX remove this once tiling is properly supported */
- array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
- V_0280A0_ARRAY_1D_TILED_THIN1;
-
- /* XXX quite sure for dx10+ hw don't need any offset hacks */
- offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
- level, state->zsbuf->u.tex.first_layer);
- pitch = rtex->pitch_in_blocks[level] / 8 - 1;
- slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
- if (slice) {
- slice = slice - 1;
- }
- } else {
- offset = rtex->surface.level[level].offset;
- pitch = rtex->surface.level[level].nblk_x / 8 - 1;
- slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
- if (slice) {
- slice = slice - 1;
- }
- switch (rtex->surface.level[level].mode) {
- case RADEON_SURF_MODE_2D:
- array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
- break;
- case RADEON_SURF_MODE_1D:
- case RADEON_SURF_MODE_LINEAR_ALIGNED:
- case RADEON_SURF_MODE_LINEAR:
- default:
- array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
- break;
- }
+ offset = rtex->surface.level[level].offset;
+ pitch = rtex->surface.level[level].nblk_x / 8 - 1;
+ slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
+ if (slice) {
+ slice = slice - 1;
+ }
+ switch (rtex->surface.level[level].mode) {
+ case RADEON_SURF_MODE_2D:
+ array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
+ break;
+ case RADEON_SURF_MODE_1D:
+ case RADEON_SURF_MODE_LINEAR_ALIGNED:
+ case RADEON_SURF_MODE_LINEAR:
+ default:
+ array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
+ break;
}
format = r600_translate_dbformat(state->zsbuf->format);
offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice));
- if (!rscreen->use_surface_alloc) {
- r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000);
- } else {
- r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW,
- S_028004_SLICE_START(state->zsbuf->u.tex.first_layer) |
- S_028004_SLICE_MAX(state->zsbuf->u.tex.last_layer));
- }
+ r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW,
+ S_028004_SLICE_START(state->zsbuf->u.tex.first_layer) |
+ S_028004_SLICE_MAX(state->zsbuf->u.tex.last_layer));
r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO,
S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format),
&rtex->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
- (surf->aligned_height / 8) - 1);
+ (rtex->surface.level[level].nblk_y / 8) - 1);
}
static void r600_set_framebuffer_state(struct pipe_context *ctx,
unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
unsigned level, unsigned layer)
{
- unsigned offset = rtex->offset[level];
-
- switch (rtex->resource.b.b.target) {
- case PIPE_TEXTURE_3D:
- case PIPE_TEXTURE_CUBE:
- default:
- return offset + layer * rtex->layer_size[level];
- }
-}
-
-static unsigned r600_get_block_alignment(struct pipe_screen *screen,
- enum pipe_format format,
- unsigned array_mode)
-{
- struct r600_screen* rscreen = (struct r600_screen *)screen;
- unsigned pixsize = util_format_get_blocksize(format);
- int p_align;
-
- switch(array_mode) {
- case V_038000_ARRAY_1D_TILED_THIN1:
- p_align = MAX2(8,
- ((rscreen->tiling_info.group_bytes / 8 / pixsize)));
- break;
- case V_038000_ARRAY_2D_TILED_THIN1:
- p_align = MAX2(rscreen->tiling_info.num_banks,
- (((rscreen->tiling_info.group_bytes / 8 / pixsize)) *
- rscreen->tiling_info.num_banks)) * 8;
- break;
- case V_038000_ARRAY_LINEAR_ALIGNED:
- p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize);
- break;
- case V_038000_ARRAY_LINEAR_GENERAL:
- default:
- p_align = rscreen->tiling_info.group_bytes / pixsize;
- break;
- }
- return p_align;
-}
-
-static unsigned r600_get_height_alignment(struct pipe_screen *screen,
- unsigned array_mode)
-{
- struct r600_screen* rscreen = (struct r600_screen *)screen;
- int h_align;
-
- switch (array_mode) {
- case V_038000_ARRAY_2D_TILED_THIN1:
- h_align = rscreen->tiling_info.num_channels * 8;
- break;
- case V_038000_ARRAY_1D_TILED_THIN1:
- case V_038000_ARRAY_LINEAR_ALIGNED:
- h_align = 8;
- break;
- case V_038000_ARRAY_LINEAR_GENERAL:
- default:
- h_align = 1;
- break;
- }
- return h_align;
-}
-
-static unsigned r600_get_base_alignment(struct pipe_screen *screen,
- enum pipe_format format,
- unsigned array_mode)
-{
- struct r600_screen* rscreen = (struct r600_screen *)screen;
- unsigned pixsize = util_format_get_blocksize(format);
- int p_align = r600_get_block_alignment(screen, format, array_mode);
- int h_align = r600_get_height_alignment(screen, array_mode);
- int b_align;
-
- switch (array_mode) {
- case V_038000_ARRAY_2D_TILED_THIN1:
- b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize,
- p_align * pixsize * h_align);
- break;
- case V_038000_ARRAY_1D_TILED_THIN1:
- case V_038000_ARRAY_LINEAR_ALIGNED:
- case V_038000_ARRAY_LINEAR_GENERAL:
- default:
- b_align = rscreen->tiling_info.group_bytes;
- break;
- }
- return b_align;
+ return rtex->offset[level] + layer * rtex->layer_size[level];
}
static unsigned mip_minify(unsigned size, unsigned level)
return val;
}
-static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
- struct r600_resource_texture *rtex,
- unsigned level)
-{
- struct pipe_resource *ptex = &rtex->resource.b.b;
- unsigned nblocksx, block_align, width;
- unsigned blocksize = util_format_get_blocksize(rtex->real_format);
-
- if (rtex->pitch_override)
- return rtex->pitch_override / blocksize;
-
- width = mip_minify(ptex->width0, level);
- nblocksx = util_format_get_nblocksx(rtex->real_format, width);
-
- block_align = r600_get_block_alignment(screen, rtex->real_format,
- rtex->array_mode[level]);
- nblocksx = align(nblocksx, block_align);
- return nblocksx;
-}
-
-static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
- struct r600_resource_texture *rtex,
- unsigned level)
-{
- struct pipe_resource *ptex = &rtex->resource.b.b;
- unsigned height, tile_height;
-
- height = mip_minify(ptex->height0, level);
- height = util_format_get_nblocksy(rtex->real_format, height);
- tile_height = r600_get_height_alignment(screen,
- rtex->array_mode[level]);
-
- /* XXX Hack around an alignment issue. Less tests fail with this.
- *
- * The thing is depth-stencil buffers should be tiled, i.e.
- * the alignment should be >=8. If I make them tiled, stencil starts
- * working because it no longer overlaps with the depth buffer
- * in memory, but texturing like drawpix-stencil breaks. */
- if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8)
- tile_height = 8;
-
- height = align(height, tile_height);
- return height;
-}
-
-static void r600_texture_set_array_mode(struct pipe_screen *screen,
- struct r600_resource_texture *rtex,
- unsigned level, unsigned array_mode)
-{
- struct pipe_resource *ptex = &rtex->resource.b.b;
-
- switch (array_mode) {
- case V_0280A0_ARRAY_LINEAR_GENERAL:
- case V_0280A0_ARRAY_LINEAR_ALIGNED:
- case V_0280A0_ARRAY_1D_TILED_THIN1:
- default:
- rtex->array_mode[level] = array_mode;
- break;
- case V_0280A0_ARRAY_2D_TILED_THIN1:
- {
- unsigned w, h, tile_height, tile_width;
-
- tile_height = r600_get_height_alignment(screen, array_mode);
- tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode);
-
- w = mip_minify(ptex->width0, level);
- h = mip_minify(ptex->height0, level);
- if (w <= tile_width || h <= tile_height)
- rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
- else
- rtex->array_mode[level] = array_mode;
- }
- break;
- }
-}
-
static int r600_init_surface(struct r600_screen *rscreen,
struct radeon_surface *surface,
const struct pipe_resource *ptex,
return 0;
}
-static void r600_setup_miptree(struct pipe_screen *screen,
- struct r600_resource_texture *rtex,
- unsigned array_mode)
-{
- struct pipe_resource *ptex = &rtex->resource.b.b;
- enum chip_class chipc = ((struct r600_screen*)screen)->chip_class;
- unsigned size, layer_size, i, offset;
- unsigned nblocksx, nblocksy;
-
- for (i = 0, offset = 0; i <= ptex->last_level; i++) {
- unsigned blocksize = util_format_get_blocksize(rtex->real_format);
- unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode);
-
- r600_texture_set_array_mode(screen, rtex, i, array_mode);
-
- nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
- nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
-
- if (chipc >= EVERGREEN && array_mode == V_038000_ARRAY_LINEAR_GENERAL)
- layer_size = align(nblocksx, 64) * nblocksy * blocksize;
- else
- layer_size = nblocksx * nblocksy * blocksize;
-
- if (ptex->target == PIPE_TEXTURE_CUBE) {
- if (chipc >= R700)
- size = layer_size * 8;
- else
- size = layer_size * 6;
- }
- else if (ptex->target == PIPE_TEXTURE_3D)
- size = layer_size * u_minify(ptex->depth0, i);
- else
- size = layer_size * ptex->array_size;
-
- /* align base image and start of miptree */
- if ((i == 0) || (i == 1))
- offset = align(offset, base_align);
- rtex->offset[i] = offset;
- rtex->layer_size[i] = layer_size;
- rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
- rtex->pitch_in_bytes[i] = nblocksx * blocksize;
-
- offset += size;
- }
- rtex->size = offset;
-}
-
static boolean r600_texture_get_handle(struct pipe_screen* screen,
struct pipe_resource *ptex,
struct winsys_handle *whandle)
if (rtex->flushed_depth_texture)
pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
- if (rtex->stencil)
- pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL);
-
pb_reference(&resource->buf, NULL);
FREE(rtex);
}
rtex->pitch_override = pitch_in_bytes_override;
rtex->real_format = base->format;
- /* We must split depth and stencil into two separate buffers on Evergreen. */
- if ((base->bind & PIPE_BIND_DEPTH_STENCIL) &&
- ((struct r600_screen*)screen)->chip_class >= EVERGREEN &&
- util_format_is_depth_and_stencil(base->format) &&
- !rscreen->use_surface_alloc) {
- struct pipe_resource stencil;
- unsigned stencil_pitch_override = 0;
-
- switch (base->format) {
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- rtex->real_format = PIPE_FORMAT_Z24X8_UNORM;
- break;
- case PIPE_FORMAT_S8_UINT_Z24_UNORM:
- rtex->real_format = PIPE_FORMAT_X8Z24_UNORM;
- break;
- case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- rtex->real_format = PIPE_FORMAT_Z32_FLOAT;
- break;
- default:
- assert(0);
- FREE(rtex);
- return NULL;
- }
-
- /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
- if (pitch_in_bytes_override) {
- assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT ||
- base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM);
- stencil_pitch_override = pitch_in_bytes_override / 4;
- }
-
- /* Allocate the stencil buffer. */
- stencil = *base;
- stencil.format = PIPE_FORMAT_S8_UINT;
- rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode,
- stencil_pitch_override,
- max_buffer_size, NULL, FALSE, surface);
- if (!rtex->stencil) {
- FREE(rtex);
- return NULL;
- }
- /* Proceed in creating the depth buffer. */
- }
-
/* don't include stencil-only formats which we don't support for rendering */
rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
- r600_setup_miptree(screen, rtex, array_mode);
- if (rscreen->use_surface_alloc) {
- rtex->surface = *surface;
- r = r600_setup_surface(screen, rtex, array_mode,
- pitch_in_bytes_override);
- if (r) {
- FREE(rtex);
- return NULL;
- }
- }
-
- /* If we initialized separate stencil for Evergreen. place it after depth. */
- if (rtex->stencil) {
- unsigned stencil_align, stencil_offset;
-
- stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode);
- stencil_offset = align(rtex->size, stencil_align);
-
- for (unsigned i = 0; i <= rtex->stencil->resource.b.b.last_level; i++)
- rtex->stencil->offset[i] += stencil_offset;
-
- rtex->size = stencil_offset + rtex->stencil->size;
+ rtex->surface = *surface;
+ r = r600_setup_surface(screen, rtex, array_mode,
+ pitch_in_bytes_override);
+ if (r) {
+ FREE(rtex);
+ return NULL;
}
/* Now create the backing buffer. */
if (!buf && alloc_bo) {
- struct pipe_resource *ptex = &rtex->resource.b.b;
- unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
-
- if (rscreen->use_surface_alloc) {
- base_align = rtex->surface.bo_alignment;
- } else if (util_format_is_depth_or_stencil(rtex->real_format)) {
- /* ugly work around depth buffer need stencil room at end of bo */
- rtex->size += ptex->width0 * ptex->height0;
- }
+ unsigned base_align = rtex->surface.bo_alignment;
+
if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
- pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL);
FREE(rtex);
return NULL;
}
resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
}
-
- if (rtex->stencil) {
- pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf);
- rtex->stencil->resource.cs_buf = rtex->resource.cs_buf;
- rtex->stencil->resource.domains = rtex->resource.domains;
- }
return rtex;
}
int r;
if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) {
- if (rscreen->use_surface_alloc &&
- !(templ->bind & PIPE_BIND_SCANOUT) &&
+ if (!(templ->bind & PIPE_BIND_SCANOUT) &&
templ->usage != PIPE_USAGE_STAGING &&
templ->usage != PIPE_USAGE_STREAM) {
array_mode = V_038000_ARRAY_2D_TILED_THIN1;
struct pipe_resource *texture,
const struct pipe_surface *surf_tmpl)
{
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
unsigned level = surf_tmpl->u.tex.level;
surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
surface->base.u.tex.level = level;
-
- surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
- rtex, level);
return &surface->base;
}
projects / mesa.git / commitdiff