Merge ktlim@zizzer:/bk/newmem

into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

configs/example/fs.py:
configs/example/se.py:
src/mem/tport.hh:
    Hand merge.

--HG--
extra : convert_revision : b9df95534d43b3b311f24ae24717371d03d615bf

diff --cc configs/example/fs.py
index 3ce4638791a6693aaf52ad144053ed6d7ea6c971,26089aa16d7593ae146167518e4994c111959fc2..67c3912ef3e5580202f644f114ad81479285750f
--- 1/configs/example/fs.py
--- 2/configs/example/fs.py
+++ b/configs/example/fs.py
@@@ -104,10 -134,9 +104,9 @@@ np = options.num_cpu
  test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
  for i in xrange(np):
      if options.caches and not options.standard_switch:
 -        test_sys.cpu[i].addPrivateSplitL1Caches(MyCache(size = '32kB'),
 -                                                  MyCache(size = '64kB'))
 +        test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
 +                                                L1Cache(size = '64kB'))
      test_sys.cpu[i].connectMemPorts(test_sys.membus)
-     test_sys.cpu[i].mem = test_sys.physmem
  
  if len(bm) == 2:
      drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])

diff --cc configs/example/se.py
index 83c2b1f8dd51904740c3e8c5f1035e8045c5a626,7261aeb3470d9c3ca778a67dc23c8fc609d63406..1d92eb954bafbe6b4c5072ad7632f16046990c90
--- 1/configs/example/se.py
--- 2/configs/example/se.py
+++ b/configs/example/se.py
@@@ -94,33 -117,156 +94,32 @@@ if options.detailed
  
  
  if options.timing:
 -    cpu = TimingSimpleCPU()
 +    CPUClass = TimingSimpleCPU
 +    test_mem_mode = 'timing'
  elif options.detailed:
 -    cpu = DerivO3CPU()
 +    CPUClass = DerivO3CPU
 +    test_mem_mode = 'timing'
  else:
 -    cpu = AtomicSimpleCPU()
 -
 -cpu.workload = process
 -cpu.cpu_id = 0
 -
 -system = System(cpu = cpu,
 -                physmem = PhysicalMemory(range=AddrRange("512MB")),
 -                membus = Bus())
 -system.physmem.port = system.membus.port
 -system.cpu.connectMemPorts(system.membus)
 -system.cpu.clock = '2GHz'
 -if options.caches and not options.standard_switch:
 -    system.cpu.addPrivateSplitL1Caches(MyCache(size = '32kB'),
 -                                       MyCache(size = '64kB'))
 -
 -root = Root(system = system)
 -
 -if options.timing or options.detailed:
 -    root.system.mem_mode = 'timing'
 -
 -if options.standard_switch:
 -    switch_cpu = TimingSimpleCPU(defer_registration=True, cpu_id=1)
 -    switch_cpu1 = DerivO3CPU(defer_registration=True, cpu_id=2)
 -    switch_cpu.system =  system
 -    switch_cpu1.system =  system
 -    switch_cpu.clock = cpu.clock
 -    switch_cpu1.clock = cpu.clock
 -    if options.caches:
 -        switch_cpu.addPrivateSplitL1Caches(MyCache(size = '32kB'),
 -                                           MyCache(size = '64kB'))
 -
 -    switch_cpu.workload = process
 -    switch_cpu1.workload = process
 -    switch_cpu.connectMemPorts(system.membus)
 -    root.switch_cpu = switch_cpu
 -    root.switch_cpu1 = switch_cpu1
 -    switch_cpu_list = [(system.cpu, switch_cpu)]
 -    switch_cpu_list1 = [(switch_cpu, switch_cpu1)]
 -
 -# instantiate configuration
 -m5.instantiate(root)
 -
 -if options.checkpoint_dir:
 -    cptdir = options.checkpoint_dir
 -else:
 -    cptdir = getcwd()
 -
 -if options.checkpoint_restore:
 -    from os.path import isdir
 -    from os import listdir, getcwd
 -    import re
 +    CPUClass = AtomicSimpleCPU
 +    test_mem_mode = 'atomic'
  
 -    if not isdir(cptdir):
 -        m5.panic("checkpoint dir %s does not exist!" % cptdir)
 +CPUClass.clock = '2GHz'
  
 -    dirs = listdir(cptdir)
 -    expr = re.compile('cpt.([0-9]*)')
 -    cpts = []
 -    for dir in dirs:
 -        match = expr.match(dir)
 -        if match:
 -            cpts.append(match.group(1))
 +np = options.num_cpus
  
 -    cpts.sort(lambda a,b: cmp(long(a), long(b)))
 -
 -    if options.checkpoint_restore > len(cpts):
 -        m5.panic('Checkpoint %d not found' % options.checkpoint_restore)
 -
 -    print "restoring checkpoint from ","/".join([cptdir, "cpt.%s" % cpts[options.checkpoint_restore - 1]])
 -    m5.restoreCheckpoint(root, "/".join([cptdir, "cpt.%s" % cpts[options.checkpoint_restore - 1]]))
 -
 -if options.standard_switch:
 -    exit_event = m5.simulate(10000)
 -    ## when you change to Timing (or Atomic), you halt the system given
 -    ## as argument.  When you are finished with the system changes
 -    ## (including switchCpus), you must resume the system manually.
 -    ## You DON'T need to resume after just switching CPUs if you haven't
 -    ## changed anything on the system level.
 -    m5.changeToTiming(system)
 -    m5.switchCpus(switch_cpu_list)
 -    m5.resume(system)
 -
 -    exit_event = m5.simulate(500000000000)
 -    m5.switchCpus(switch_cpu_list1)
 -
 -if options.maxtick:
 -    maxtick = options.maxtick
 -elif options.maxtime:
 -    simtime = int(options.maxtime * root.clock.value)
 -    print "simulating for: ", simtime
 -    maxtick = simtime
 -else:
 -    maxtick = -1
 -
 -num_checkpoints = 0
 -
 -exit_cause = ''
 -
 -if options.take_checkpoints:
 -    [when, period] = options.take_checkpoints.split(",", 1)
 -    when = int(when)
 -    period = int(period)
 -
 -    exit_event = m5.simulate(when)
 -    while exit_event.getCause() == "checkpoint":
 -        exit_event = m5.simulate(when - m5.curTick())
 -
 -    if exit_event.getCause() == "simulate() limit reached":
 -        m5.checkpoint(root, cptdir + "cpt.%d")
 -        num_checkpoints += 1
 -
 -    sim_ticks = when
 -    exit_cause = "maximum %d checkpoints dropped" % options.max_checkpoints
 -    while num_checkpoints < options.max_checkpoints:
 -        if (sim_ticks + period) > maxtick and maxtick != -1:
 -            exit_event = m5.simulate(maxtick - sim_ticks)
 -            exit_cause = exit_event.getCause()
 -            break
 -        else:
 -            exit_event = m5.simulate(period)
 -            sim_ticks += period
 -            while exit_event.getCause() == "checkpoint":
 -                exit_event = m5.simulate(period - m5.curTick())
 -            if exit_event.getCause() == "simulate() limit reached":
 -                m5.checkpoint(root, cptdir + "cpt.%d")
 -                num_checkpoints += 1
 -
 -else: #no checkpoints being taken via this script
 -    exit_event = m5.simulate(maxtick)
 -
 -    while exit_event.getCause() == "checkpoint":
 -        m5.checkpoint(root, cptdir + "cpt.%d")
 -        num_checkpoints += 1
 -        if num_checkpoints == options.max_checkpoints:
 -            exit_cause =  "maximum %d checkpoints dropped" % options.max_checkpoints
 -            break
 -
 -        if maxtick == -1:
 -            exit_event = m5.simulate(maxtick)
 -        else:
 -            exit_event = m5.simulate(maxtick - m5.curTick())
 +system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
 +                physmem = PhysicalMemory(range=AddrRange("512MB")),
 +                membus = Bus(), mem_mode = test_mem_mode)
  
 -        exit_cause = exit_event.getCause()
 +system.physmem.port = system.membus.port
  
 -if exit_cause == '':
 -    exit_cause = exit_event.getCause()
 -print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause
 +for i in xrange(np):
 +    if options.caches and not options.standard_switch:
 +        system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
 +                                              L1Cache(size = '64kB'))
 +    system.cpu[i].connectMemPorts(system.membus)
-     system.cpu[i].mem = system.physmem
 +    system.cpu[i].workload = process
  
 +root = Root(system = system)
  
 +Simulation.run(options, root, system)

diff --cc src/cpu/ozone/front_end_impl.hh
Simple merge

diff --cc src/cpu/ozone/thread_state.hh
Simple merge

diff --cc src/cpu/simple/atomic.cc
Simple merge

diff --cc src/cpu/simple/base.cc
Simple merge

diff --cc src/cpu/thread_state.cc
Simple merge

diff --cc src/mem/tport.hh
index 438ec56dcfcc14ce11a32ccfb819bc8f62add262,b419b7c7f4e99c0ef731d5e78a8aeedc7cdf3726..3d28ea3e5d65d0221e468396ca836d3d9ff79d18
--- 1/src/mem/tport.hh
--- 2/src/mem/tport.hh
+++ b/src/mem/tport.hh
@@@ -114,8 -117,8 +114,8 @@@ class SimpleTimingPort : public Por
  
    public:
  
-     SimpleTimingPort(std::string pname)
-         : Port(pname), sendEvent(this), drainEvent(NULL)
+     SimpleTimingPort(std::string pname, MemObject *_owner = NULL)
 -        : Port(pname, _owner), outTiming(0), drainEvent(NULL)
++        : Port(pname, _owner), sendEvent(this), drainEvent(NULL)
      {}
  
      /** Hook for draining timing accesses from the system.  The