trying to get ISA to parse correctly ...
authorKorey Sewell <ksewell@umich.edu>
Wed, 15 Feb 2006 02:26:01 +0000 (21:26 -0500)
committerKorey Sewell <ksewell@umich.edu>
Wed, 15 Feb 2006 02:26:01 +0000 (21:26 -0500)
arch/mips/isa/formats/unimp.isa:
    holds unimplemented formats
arch/mips/isa/formats/unknown.isa:
    holds unknown formats

--HG--
extra : convert_revision : 0f3a8ea7e3a1592322cce54527d6989152e57975

arch/mips/isa/decoder.isa
arch/mips/isa/formats.isa
arch/mips/isa/formats/basic.isa
arch/mips/isa/formats/branch.isa
arch/mips/isa/formats/int.isa
arch/mips/isa/formats/unimp.isa [new file with mode: 0644]
arch/mips/isa/formats/unknown.isa [new file with mode: 0644]
arch/mips/isa/main.isa

index 2ec7da805b18e1d7b7c924baf6f101cba46a324d..7e7dfe1d10627031a71761a8f3ef065f502ebee0 100644 (file)
@@ -9,7 +9,7 @@
 //
 //@todo: Distinguish "unknown/future" use insts from "reserved"
 // ones
-decode OPCODE_HI default FailUnimpl::unknown() {
+decode OPCODE_HI default Unknown::unknown() {
 
     // Derived From ... Table A-2 MIPS32 ISA Manual
     0x0: decode OPCODE_LO default FailUnimpl::reserved(){
@@ -66,10 +66,11 @@ decode OPCODE_HI default FailUnimpl::unknown() {
                 0x3: movn({{ if (Rt != 0) Rd = Rs; }});
               }
 
+
               format WarnUnimpl {
-                0x4: syscall({{ xc->syscall()}},IsNonSpeculative);
-                0x5: break({{ }});
-                0x7: sync({{ }});
+                0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative
+                0x5: break();
+                0x7: sync();
               }
             }
 
@@ -80,14 +81,14 @@ decode OPCODE_HI default FailUnimpl::unknown() {
                 0x2: mflo({{ Rd = xc->miscRegs.lo; }});
                 0x3: mtlo({{ xc->miscRegs.lo = Rs; }});
               }
-            };
+            }
 
             0x3: decode FUNCTION_LO {
               format IntOp {
                 0x0: mult({{
                         INT64 temp1 = Rs.sw * Rt.sw;
                         xc->miscRegs.hi->temp1<63:32>;
-                        xc->miscRegs.lo->temp1<31:0>
+                        xc->miscRegs.lo->temp1<31:0>;
                 }});
 
                 0x1: multu({{
index 404314c7a7e8993f4fc69e8fca18e5d656ee9514..20ef49d82e1a8451bb53fb7a8a29c5b6d93ba0d0 100644 (file)
@@ -1,22 +1,29 @@
 //Include the basic format
 //Templates from this format are used later
-##include "m5/arch/mips/isa_desc/formats/basic.format"
+##include "m5/arch/mips/isa/formats/basic.isa"
 
 //Include the integerOp and integerOpCc format
-##include "m5/arch/mips/isa_desc/formats/integerop.format"
+##include "m5/arch/mips/isa/formats/int.isa"
 
 //Include the floatOp format
-##include "m5/arch/mips/isa_desc/formats/floatop.format"
+##include "m5/arch/mips/isa/formats/fp.isa"
 
 //Include the mem format
-##include "m5/arch/mips/isa_desc/formats/mem.format"
+##include "m5/arch/mips/isa/formats/mem.isa"
 
 //Include the trap format
-##include "m5/arch/mips/isa_desc/formats/trap.format"
+##include "m5/arch/mips/isa/formats/trap.isa"
 
 //Include the branch format
-##include "m5/arch/mips/isa_desc/formats/branch.format"
+##include "m5/arch/mips/isa/formats/branch.isa"
 
 //Include the noop format
-##include "m5/arch/mips/isa_desc/formats/noop.format"
+##include "m5/arch/mips/isa/formats/noop.isa"
+
+
+//Include the noop format
+##include "m5/arch/mips/isa/formats/unimp.isa"
+
+//Include the noop format
+##include "m5/arch/mips/isa/formats/unknown.isa"
 
index 8fba9845a52276a57f1eb0cdbf9990ea0e9cbc29..fc97c6ffa32d670bf1a61235d3e18c0649d572ae 100644 (file)
@@ -56,7 +56,7 @@ def template BasicDecodeWithMnemonic {{
 }};
 
 // The most basic instruction format... used only for a few misc. insts
-def format BasicOperate(code, *flags) {{
+def format BasicOp(code, *flags) {{
         iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
index a565eb71bf602e29ab811568d7afa92fbedbab24..e9c790c53b1d902132bb9e20af1684b3359a391a 100644 (file)
-////////////////////////////////////////////////////////////////////
+// -*- mode:c++ -*-
+
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// All rights reserved.
 //
-// Branch instructions
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
 //
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 output header {{
-        /**
-         * Base class for integer operations.
-         */
-        class Branch : public MipsStaticInst
+
+    /**
+     * Base class for instructions whose disassembly is not purely a
+     * function of the machine instruction (i.e., it depends on the
+     * PC).  This class overrides the disassemble() method to check
+     * the PC and symbol table values before re-using a cached
+     * disassembly string.  This is necessary for branches and jumps,
+     * where the disassembly string includes the target address (which
+     * may depend on the PC and/or symbol table).
+     */
+    class PCDependentDisassembly : public AlphaStaticInst
+    {
+      protected:
+        /// Cached program counter from last disassembly
+        mutable Addr cachedPC;
+        /// Cached symbol table pointer from last disassembly
+        mutable const SymbolTable *cachedSymtab;
+
+        /// Constructor
+        PCDependentDisassembly(const char *mnem, MachInst _machInst,
+                               OpClass __opClass)
+            : AlphaStaticInst(mnem, _machInst, __opClass),
+              cachedPC(0), cachedSymtab(0)
         {
-                protected:
+        }
 
-                /// Constructor
-                Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
-                {
-                }
+        const std::string &
+        disassemble(Addr pc, const SymbolTable *symtab) const;
+    };
 
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-        };
-}};
+    /**
+     * Base class for branches (PC-relative control transfers),
+     * conditional or unconditional.
+     */
+    class Branch : public PCDependentDisassembly
+    {
+      protected:
+        /// Displacement to target address (signed).
+        int32_t disp;
 
-output decoder {{
-        std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        /// Constructor.
+        Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
+            : PCDependentDisassembly(mnem, _machInst, __opClass),
+              disp(BRDISP << 2)
+        {
+        }
+
+        Addr branchTarget(Addr branchPC) const;
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+
+    /**
+     * Base class for jumps (register-indirect control transfers).  In
+     * the Alpha ISA, these are always unconditional.
+     */
+    class Jump : public PCDependentDisassembly
+    {
+      protected:
+
+        /// Displacement to target address (signed).
+        int32_t disp;
+
+      public:
+        /// Constructor
+        Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
+            : PCDependentDisassembly(mnem, _machInst, __opClass),
+              disp(BRDISP)
         {
-                return "Disassembly of integer instruction\n";
         }
+
+        Addr branchTarget(ExecContext *xc) const;
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
 }};
 
-def template BranchExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+output decoder {{
+    Addr
+    Branch::branchTarget(Addr branchPC) const
+    {
+        return branchPC + 4 + disp;
+    }
+
+    Addr
+    Jump::branchTarget(ExecContext *xc) const
+    {
+        Addr NPC = xc->readPC() + 4;
+        uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
+        return (Rb & ~3) | (NPC & 1);
+    }
+
+    const std::string &
+    PCDependentDisassembly::disassemble(Addr pc,
+                                        const SymbolTable *symtab) const
+    {
+        if (!cachedDisassembly ||
+            pc != cachedPC || symtab != cachedSymtab)
         {
-                //Attempt to execute the instruction
-                try
-                {
-                        checkPriv;
-
-                        %(op_decl)s;
-                        %(op_rd)s;
-                        %(code)s;
-                }
-                //If we have an exception for some reason,
-                //deal with it
-                catch(MipsException except)
-                {
-                        //Deal with exception
-                        return No_Fault;
-                }
-
-                //Write the resulting state to the execution context
-                %(op_wb)s;
-
-                return No_Fault;
+            if (cachedDisassembly)
+                delete cachedDisassembly;
+
+            cachedDisassembly =
+                new std::string(generateDisassembly(pc, symtab));
+            cachedPC = pc;
+            cachedSymtab = symtab;
+        }
+
+        return *cachedDisassembly;
+    }
+
+    std::string
+    Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+
+        ccprintf(ss, "%-10s ", mnemonic);
+
+        // There's only one register arg (RA), but it could be
+        // either a source (the condition for conditional
+        // branches) or a destination (the link reg for
+        // unconditional branches)
+        if (_numSrcRegs > 0) {
+            printReg(ss, _srcRegIdx[0]);
+            ss << ",";
+        }
+        else if (_numDestRegs > 0) {
+            printReg(ss, _destRegIdx[0]);
+            ss << ",";
         }
+
+#ifdef SS_COMPATIBLE_DISASSEMBLY
+        if (_numSrcRegs == 0 && _numDestRegs == 0) {
+            printReg(ss, 31);
+            ss << ",";
+        }
+#endif
+
+        Addr target = pc + 4 + disp;
+
+        std::string str;
+        if (symtab && symtab->findSymbol(target, str))
+            ss << str;
+        else
+            ccprintf(ss, "0x%x", target);
+
+        return ss.str();
+    }
+
+    std::string
+    Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+
+        ccprintf(ss, "%-10s ", mnemonic);
+
+#ifdef SS_COMPATIBLE_DISASSEMBLY
+        if (_numDestRegs == 0) {
+            printReg(ss, 31);
+            ss << ",";
+        }
+#endif
+
+        if (_numDestRegs > 0) {
+            printReg(ss, _destRegIdx[0]);
+            ss << ",";
+        }
+
+        ccprintf(ss, "(r%d)", RB);
+
+        return ss.str();
+    }
+}};
+
+def template JumpOrBranchDecode {{
+    return (RA == 31)
+        ? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
+        : (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
 }};
 
 def format CondBranch(code) {{
@@ -64,3 +219,41 @@ def format CondBranch(code) {{
     exec_output = BasicExecute.subst(iop)
 }};
 
+let {{
+def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
+    # Declare basic control transfer w/o link (i.e. link reg is R31)
+    nolink_code = 'NPC = %s;\n' % npc_expr
+    nolink_iop = InstObjParams(name, Name, base_class,
+                               CodeBlock(nolink_code), flags)
+    header_output = BasicDeclare.subst(nolink_iop)
+    decoder_output = BasicConstructor.subst(nolink_iop)
+    exec_output = BasicExecute.subst(nolink_iop)
+
+    # Generate declaration of '*AndLink' version, append to decls
+    link_code = 'Ra = NPC & ~3;\n' + nolink_code
+    link_iop = InstObjParams(name, Name + 'AndLink', base_class,
+                             CodeBlock(link_code), flags)
+    header_output += BasicDeclare.subst(link_iop)
+    decoder_output += BasicConstructor.subst(link_iop)
+    exec_output += BasicExecute.subst(link_iop)
+
+    # need to use link_iop for the decode template since it is expecting
+    # the shorter version of class_name (w/o "AndLink")
+
+    return (header_output, decoder_output,
+            JumpOrBranchDecode.subst(nolink_iop), exec_output)
+}};
+
+def format UncondBranch(*flags) {{
+    flags += ('IsUncondControl', 'IsDirectControl')
+    (header_output, decoder_output, decode_block, exec_output) = \
+        UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
+}};
+
+def format Jump(*flags) {{
+    flags += ('IsUncondControl', 'IsIndirectControl')
+    (header_output, decoder_output, decode_block, exec_output) = \
+        UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
+}};
+
+
index 5b8df54e9dec42299982550c15c2311d3c821bcd..521f3a1306f0a365a6d50c173a5e78ad759ee384 100644 (file)
@@ -53,9 +53,9 @@ def format IntOp(code, *opt_flags) {{
         orig_code = code
         cblk = CodeBlock(code)
 
-        //Figure out if we are creating a IntImmOp or a IntOp
+        Figure out if we are creating a IntImmOp or a IntOp
         strlen = len(name)
-        if ( name[strlen-1] = 'i' or ( name[strlen-2:] = 'iu'))
+        if name[strlen-1] == 'i' or name[strlen-2:] == 'iu':
                 iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
         else:
                 iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
diff --git a/arch/mips/isa/formats/unimp.isa b/arch/mips/isa/formats/unimp.isa
new file mode 100644 (file)
index 0000000..7678881
--- /dev/null
@@ -0,0 +1,165 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+output header {{
+    /**
+     * Static instruction class for unimplemented instructions that
+     * cause simulator termination.  Note that these are recognized
+     * (legal) instructions that the simulator does not support; the
+     * 'Unknown' class is used for unrecognized/illegal instructions.
+     * This is a leaf class.
+     */
+    class FailUnimplemented : public AlphaStaticInst
+    {
+      public:
+        /// Constructor
+        FailUnimplemented(const char *_mnemonic, MachInst _machInst)
+            : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
+        {
+            // don't call execute() (which panics) if we're on a
+            // speculative path
+            flags[IsNonSpeculative] = true;
+        }
+
+        %(BasicExecDeclare)s
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+
+    /**
+     * Base class for unimplemented instructions that cause a warning
+     * to be printed (but do not terminate simulation).  This
+     * implementation is a little screwy in that it will print a
+     * warning for each instance of a particular unimplemented machine
+     * instruction, not just for each unimplemented opcode.  Should
+     * probably make the 'warned' flag a static member of the derived
+     * class.
+     */
+    class WarnUnimplemented : public AlphaStaticInst
+    {
+      private:
+        /// Have we warned on this instruction yet?
+        mutable bool warned;
+
+      public:
+        /// Constructor
+        WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
+            : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
+        {
+            // don't call execute() (which panics) if we're on a
+            // speculative path
+            flags[IsNonSpeculative] = true;
+        }
+
+        %(BasicExecDeclare)s
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+}};
+
+output decoder {{
+    std::string
+    FailUnimplemented::generateDisassembly(Addr pc,
+                                           const SymbolTable *symtab) const
+    {
+        return csprintf("%-10s (unimplemented)", mnemonic);
+    }
+
+    std::string
+    WarnUnimplemented::generateDisassembly(Addr pc,
+                                           const SymbolTable *symtab) const
+    {
+#ifdef SS_COMPATIBLE_DISASSEMBLY
+        return csprintf("%-10s", mnemonic);
+#else
+        return csprintf("%-10s (unimplemented)", mnemonic);
+#endif
+    }
+}};
+
+output exec {{
+    Fault
+    FailUnimplemented::execute(%(CPU_exec_context)s *xc,
+                               Trace::InstRecord *traceData) const
+    {
+        panic("attempt to execute unimplemented instruction '%s' "
+              "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
+        return Unimplemented_Opcode_Fault;
+    }
+
+    Fault
+    WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
+                               Trace::InstRecord *traceData) const
+    {
+        if (!warned) {
+            warn("instruction '%s' unimplemented\n", mnemonic);
+            warned = true;
+        }
+
+        return No_Fault;
+    }
+}};
+
+
+def format FailUnimpl() {{
+    iop = InstObjParams(name, 'FailUnimplemented')
+    decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
+
+def format WarnUnimpl() {{
+    iop = InstObjParams(name, 'WarnUnimplemented')
+    decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
+
+output header {{
+    /**
+     * Static instruction class for unknown (illegal) instructions.
+     * These cause simulator termination if they are executed in a
+     * non-speculative mode.  This is a leaf class.
+     */
+    class Unknown : public AlphaStaticInst
+    {
+      public:
+        /// Constructor
+        Unknown(MachInst _machInst)
+            : AlphaStaticInst("unknown", _machInst, No_OpClass)
+        {
+            // don't call execute() (which panics) if we're on a
+            // speculative path
+            flags[IsNonSpeculative] = true;
+        }
+
+        %(BasicExecDeclare)s
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+}};
+
diff --git a/arch/mips/isa/formats/unknown.isa b/arch/mips/isa/formats/unknown.isa
new file mode 100644 (file)
index 0000000..6eba5b4
--- /dev/null
@@ -0,0 +1,52 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+output decoder {{
+    std::string
+    Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
+                        "unknown", machInst, OPCODE);
+    }
+}};
+
+output exec {{
+    Fault
+    Unknown::execute(%(CPU_exec_context)s *xc,
+                     Trace::InstRecord *traceData) const
+    {
+        panic("attempt to execute unknown instruction "
+              "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
+        return Unimplemented_Opcode_Fault;
+    }
+}};
+
+def format Unknown() {{
+    decode_block = 'return new Unknown(machInst);\n'
+}};
+
index a8c71872beff11b88fa1ea2d95d3fd58b34b9b77..411e398b49cb863e170ef5f3b988bcfcb71d2e20 100644 (file)
@@ -26,7 +26,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-##include "m5/arch/sparc/isa_desc/includes.h"
+##include "m5/arch/mips/isa/includes.isa"
 
 ////////////////////////////////////////////////////////////////////
 //
 namespace MipsISA;
 
 //Include the bitfield definitions
-##include "m5/arch/mips/isa_desc/bitfields.h"
+##include "m5/arch/mips/isa/bitfields.isa"
 
 //Include the operand_types and operand definitions
-##include "m5/arch/mips/isa_desc/operands.h"
+##include "m5/arch/mips/isa/operands.isa"
 
 //Include the base class for mips instructions, and some support code
-##include "m5/arch/mips/isa_desc/base.h"
+##include "m5/arch/mips/isa/base.isa"
 
 //Include the definitions for the instruction formats
-##include "m5/arch/mips/isa_desc/formats.h"
+##include "m5/arch/mips/isa/formats.isa"
 
 //Include the decoder definition
-##include "m5/arch/mips/isa_desc/decoder.h"
+##include "m5/arch/mips/isa/decoder.isa"