mention ls011 in svp64 page, intention to move LD/ST-postinc to EXT2xx

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 05f48b07439c817d0935aecb776cd16b45103686..b4dbea506109d5b6ec30a695ae9c99bb5b7a47af 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -65,14 +65,15 @@ of that following instruction.  **All prefixed 32-bit instructions
 (Defined Words) retain their non-prefixed encoding and definition**.
 
 Two apparent exceptions to the above hard rule exist: SV
-Branch-Conditional operations and LD/ST-update "Post-Increment" Mode.
-Post-Increment was considered sufficiently high priority (significantly
-reducing hot-loop instruction count) that one bit in the Prefix
-is reserved for it (Note the intention to release that bit and move
-Post-Increment instructions to EXT2xx).  Vectorised Branch-Conditional
-operations "embed" the original Scalar Branch-Conditional behaviour into
-a much more advanced variant that is highly suited to High-Performance
-Computation (HPC), Supercomputing, and parallel GPU Workloads.
+Branch-Conditional operations and LD/ST-update "Post-Increment"
+Mode.  Post-Increment was considered sufficiently high priority
+(significantly reducing hot-loop instruction count) that one bit in
+the Prefix is reserved for it (*Note the intention to release that bit
+and move Post-Increment instructions to EXT2xx, as part of [[ls011]]*).
+Vectorised Branch-Conditional operations "embed" the original Scalar
+Branch-Conditional behaviour into a much more advanced variant that is
+highly suited to High-Performance Computation (HPC), Supercomputing,
+and parallel GPU Workloads.
 
 *Architectural Resource Allocation note: it is prohibited to accept RFCs
 which fundamentally violate this hard requirement.  Under no circumstances