soc_core: adapt memory map for mainline Linux with mor1kx

Mainline Linux expects it to be loaded at the physical address of 0x0.
Change the MAIN_RAM base address to 0x0 and update exception vector
during the booting process.

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 976baa4cd2509051079930092d0d55c90b975ddd..c2291df6dfe7f18c25bb35c5f4230d52922157e5 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -202,6 +202,15 @@ class SoCCore(Module):
             self.soc_mem_map["csr"]  = 0x12000000
             csr_alignment = 64
 
+        # Mainline Linux OpenRISC arch code requires Linux kernel to be loaded
+        # at the physical address of 0x0. As we are running Linux from the
+        # MAIN_RAM region - move it to satisfy that requirement.
+        if cpu_type == "mor1kx" and cpu_variant == "linux":
+            self.soc_mem_map["main_ram"] = 0x00000000
+            self.soc_mem_map["rom"]      = 0x10000000
+            self.soc_mem_map["sram"]     = 0x50000000
+            self.soc_mem_map["csr"]      = 0x60000000
+
         if cpu_type == "None":
             cpu_type = None
 

diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c
index 41e179f49c37f22bfc5e881c574b4a73db438f51..559c495b75dcf043153a71ab4e6c9bc90b1465f8 100644 (file)
--- a/litex/soc/software/bios/boot.c
+++ b/litex/soc/software/bios/boot.c
@@ -43,6 +43,15 @@ static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, u
 #ifdef CONFIG_L2_SIZE
        flush_l2_cache();
 #endif
+
+#if defined(CONFIG_CPU_TYPE_MOR1KX) && defined(CONFIG_CPU_VARIANT_LINUX)
+       /* Mainline Linux expects to have exception vector base address set to the
+        * base address of Linux kernel; it also expects to be run with an offset
+        * of 0x100. */
+       mtspr(SPR_EVBAR, addr);
+       addr += 0x100;
+#endif
+
        boot_helper(r1, r2, r3, addr);
        while(1);
 }