| ISA <br>name | Num <br>opcodes | Taxonomy / <br> Class | Predicate <br> Masks | Twin <br> Predication | Explicit <br> Vector regs | 128-bit <br> operations | Bigint <br> capability | LDST <br> Fault-First | Data-dependent <br> Fail-first | Predicate-<br> Result | Matrix HW<br> support |
|----------------|-----------------|-----------------------|----------------------|-----------------------|----------------------------|-------------------------|------------------------|-----------------------|--------------------------------|-----------------------|-----------------------|
-| SVP64 | 5 (1) | Scalable (2) | yes | yes (3) | no (4) | see (5) | yes (6) | yes (7) | yes (8) | yes (9) | yes (10) |
+| Draft SVP64 | 5 (1) | Scalable (2) | yes | yes (3) | no (4) | see (5) | yes (6) | yes (7) | yes (8) | yes (9) | yes (10) |
| VSX | 700+ | Packed SIMD | no | no | yes (11) | yes | no | no | no | no | yes (12) |
| NEON | ~250 (13) | Predicated SIMD | yes | no | yes | yes | no | no | no | no | no |
| SVE2 | ~1000 (14) | Scalable HW (15) | yes | no | yes | yes | no | yes (7) | no | no | no |