+2017-10-06 Sergey Shalnov <Sergey.Shalnov@intel.com>
+
+ * config/i386/i386.md(*movsf_internal, *movdf_internal):
+ Avoid 512-bit AVX modes for TARGET_PREFER_AVX256.
+
2017-10-24 Eric Botcazou <ebotcazou@adacore.com>
PR middle-end/82569
/* movaps is one byte shorter for non-AVX targets. */
(eq_attr "alternative" "13,17")
- (cond [(ior (match_operand 0 "ext_sse_reg_operand")
- (match_operand 1 "ext_sse_reg_operand"))
+ (cond [(and (ior (not (match_test "TARGET_PREFER_AVX256"))
+ (not (match_test "TARGET_AVX512VL")))
+ (ior (match_operand 0 "ext_sse_reg_operand")
+ (match_operand 1 "ext_sse_reg_operand")))
(const_string "V8DF")
(ior (not (match_test "TARGET_SSE2"))
(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
better to maintain the whole registers in single format
to avoid problems on using packed logical operations. */
(eq_attr "alternative" "6")
- (cond [(ior (match_operand 0 "ext_sse_reg_operand")
- (match_operand 1 "ext_sse_reg_operand"))
+ (cond [(and (ior (not (match_test "TARGET_PREFER_AVX256"))
+ (not (match_test "TARGET_AVX512VL")))
+ (ior (match_operand 0 "ext_sse_reg_operand")
+ (match_operand 1 "ext_sse_reg_operand")))
(const_string "V16SF")
(ior (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
(match_test "TARGET_SSE_SPLIT_REGS"))