(no commit message)

diff --git a/openpower/sv/rfc/ls011.mdwn b/openpower/sv/rfc/ls011.mdwn
index 307db5a277b668af5b10e328c5cb072d7ebdf3aa..5dc568f3ac52ce54185f2bdbad53c69cd0d0803c 100644 (file)
--- a/openpower/sv/rfc/ls011.mdwn
+++ b/openpower/sv/rfc/ls011.mdwn
@@ -24,7 +24,8 @@ fit into one single Primary Opcode.  EXT2xx is recommended.
 
 One alternative idea is that bit 31 could be allocated (retrospectively)
 to Post-Increment.  Although it may be too late for Scalar Power ISA
-it **may** be possible to consider for SVP64Single and/or SVP64-Vector
+it **may** be possible to consider for SVP64Single and/or SVP64-Vector,
+but this risks creating a non-Orthogonal ISA.