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diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 90a96fa761148777c11d22fed02d881308fa4885..1c62b0cb0801f723135fbc392cad2f2f850ab178 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -43,6 +43,8 @@ detrimental adverse effect.
 Consequently in SV, XER.SO and CR.OV behaviour is disregarded.  XER is
 simply neither read nor written.  This includes when `scalar identity behaviour` occurs.  If OpenPOWER v3.0/1 scalar behaviour is desired then OpenPOWER v3.0/1 instructions should be used, not SV Prefixed ones.
 
+An interesting side-effect of this decision is that the OE flag is now free for other uses when SV Prefixing is used.
+
 # Register Naming and size
 
 SV Registers are simply the INT, FP and CR register files extended
@@ -793,6 +795,13 @@ hindrance, regardless of the length of VL.
 
 (see [[discussion]].  some alternative schemes are described there)
 
+### Rc=1 when SUBVL!=1
+
+sub-vectors are effectively a form of SIMD (length 2 to 4). Only 1 bit of predicate is allocated per subvector; likewise only one CR is allocated
+per subvector.
+
+This leaves a conundrum as to how to apply CR computation per subvector, when normally Rc=1 is exclusively applied to scalar elements.  A solution is to perform a bitwise OR or AND of the subvector tests.  Given that OE is ignored, rhis field may (when available) be used to select OR or AND behavior.
+
 ### Table of CR fields
 
 CR[i] is the notation used by the OpenPower spec to refer to CR field #i,