[ARM/AArch64] Improve modeled latency between FP operations and FP->GP register moves
authorKyrylo Tkachov <kyrylo.tkachov@arm.com>
Tue, 18 Nov 2014 16:26:02 +0000 (16:26 +0000)
committerKyrylo Tkachov <ktkachov@gcc.gnu.org>
Tue, 18 Nov 2014 16:26:02 +0000 (16:26 +0000)
* config/arm/cortex-a15-neon.md (cortex_a15_vfp_to_from_gp):
Split into...
(cortex_a15_gp_to_vfp): ...This.
(cortex_a15_fp_to_gp): ...And this.
Define and comment bypass from vfp operations to fp->gp moves.

From-SVN: r217725

gcc/ChangeLog
gcc/config/arm/cortex-a15-neon.md

index a15197eefc609139370029812a4c610ec7ba3bae..4a825c17310aa3e29f793554a542d55d54c6e62f 100644 (file)
@@ -1,3 +1,11 @@
+2014-11-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/arm/cortex-a15-neon.md (cortex_a15_vfp_to_from_gp):
+       Split into...
+       (cortex_a15_gp_to_vfp): ...This.
+       (cortex_a15_fp_to_gp): ...And this.
+       Define and comment bypass from vfp operations to fp->gp moves.
+
 2014-11-18  Martin Liska  <mliska@suse.cz>
 
        * var-tracking.c (vt_find_locations): New fibonacci_node is used.
index 02d4a530b2ba43b98bda9c4ab229e9ea3b50c7c3..bc09cd6a4d7f39a9b0bf24575e8af99027656c1e 100644 (file)
        (eq_attr "type" "fmov"))
   "ca15_issue1,ca15_cx_perm")
 
-(define_insn_reservation "cortex_a15_vfp_to_from_gp" 5
+(define_insn_reservation "cortex_a15_gp_to_vfp" 5
   (and (eq_attr "tune" "cortexa15")
-       (eq_attr "type" "f_mcr, f_mcrr, f_mrc, f_mrrc"))
-  "ca15_issue1,ca15_ls1+ca15_ls2")
+       (eq_attr "type" "f_mcr, f_mcrr"))
+  "ca15_issue1,ca15_ls")
+
+(define_insn_reservation "cortex_a15_mov_vfp_to_gp" 5
+  (and (eq_attr "tune" "cortexa15")
+       (eq_attr "type" "f_mrc, f_mrrc"))
+  "ca15_issue1,ca15_ls")
+
+;; Moves from floating point registers to general purpose registers
+;; induce additional latency.
+(define_bypass 10 "cortex_a15_vfp*, cortex_a15_neon*, cortex_a15_gp_to_vfp" "cortex_a15_mov_vfp_to_gp")
+
 
 (define_insn_reservation "cortex_a15_vfp_ariths" 7
   (and (eq_attr "tune" "cortexa15")