Add a new operation class for IPR accesses, and have IPR-accessing

instructions use it (instead of IntALU, as before).  Default config
has a single non-pipelined 3-cycle unit.  A bit conservative for the
ev6 (some are 1, some are 3).

arch/alpha/isa_desc:
    Make hw_mfpr and hw_mtpr use IprAccessOp op class.
cpu/full_cpu/op_class.hh:
    Add IprAccess.

--HG--
extra : convert_revision : d4103da3343a586936839e29981fd15d6930d442

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 5308efaaef5034b01bb9b5e87f6cbd5f7b080241..6a6bca4fe2b65a144218b0d1656b295c1be46131 100644 (file)
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -1610,7 +1610,8 @@ output decoder {{
 }};
 
 def format HwMoveIPR(code) {{
-    iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code))
+    iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code),
+                       ['IprAccessOp'])
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)

diff --git a/cpu/full_cpu/op_class.hh b/cpu/full_cpu/op_class.hh
index a14ccfaed404c29059f0df8b5f95a8dd3eaefae0..8e85e8d8a4e984ea0bf86624b8c84bc3b08f217a 100644 (file)
--- a/cpu/full_cpu/op_class.hh
+++ b/cpu/full_cpu/op_class.hh
@@ -51,6 +51,7 @@ enum OpClass {
     FloatSqrtOp,       /* floating point square root */
     MemReadOp,         /* memory read port */
     MemWriteOp,                /* memory write port */
+    IprAccessOp,       /* Internal Processor Register read/write port */
     InstPrefetchOp,    /* instruction prefetch port (on I-cache) */
     Num_OpClasses      /* total functional unit classes */
 };