+2013-04-25 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
+
+ * config/aarch64/aarch64.md
+ (*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>): New pattern.
+
2013-04-25 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* config/aarch64/aarch64.md (*ngc<mode>): New pattern.
(set_attr "mode" "<GPI:MODE>")]
)
+(define_insn "*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>"
+ [(set (reg:CC_SWP CC_REGNUM)
+ (compare:CC_SWP (ashift:GPI
+ (ANY_EXTEND:GPI
+ (match_operand:ALLX 0 "register_operand" "r"))
+ (match_operand:QI 1 "aarch64_shift_imm_<mode>" "n"))
+ (match_operand:GPI 2 "register_operand" "r")))]
+ ""
+ "cmp\\t%<GPI:w>2, %<GPI:w>0, <su>xt<ALLX:size> %1"
+ [(set_attr "v8type" "alus_ext")
+ (set_attr "mode" "<GPI:MODE>")]
+)
;; -------------------------------------------------------------------
;; Store-flag and conditional select insns
+2013-04-25 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
+
+ * gcc.target/aarch64/cmp.c: New.
+
2013-04-25 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* gcc.target/aarch64/ngc.c: New.
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+cmp_si_test1 (int a, int b, int c)
+{
+ if (a > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+int
+cmp_si_test2 (int a, int b, int c)
+{
+ if ((a >> 3) > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+typedef long long s64;
+
+s64
+cmp_di_test1 (s64 a, s64 b, s64 c)
+{
+ if (a > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+s64
+cmp_di_test2 (s64 a, s64 b, s64 c)
+{
+ if ((a >> 3) > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+int
+cmp_di_test3 (int a, s64 b, s64 c)
+{
+ if (a > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+int
+cmp_di_test4 (int a, s64 b, s64 c)
+{
+ if (((s64)a << 3) > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+/* { dg-final { scan-assembler-times "cmp\tw\[0-9\]+, w\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, x\[0-9\]+" 4 } } */