i965: support destination horiz strides in align1 access mode.

This is required for scatter writes in destination regions to work.

diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 207b8b7ca3824b55190f16097b4eb97a39691718..8cbe4215fbf80221455936273519924a6549962d 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -65,7 +65,7 @@ struct brw_reg
    GLuint abs:1;               /* source only */
    GLuint vstride:4;           /* source only */
    GLuint width:3;             /* src only, align1 only */
-   GLuint hstride:2;                   /* src only, align1 only */
+   GLuint hstride:2;                   /* align1 only */
    GLuint address_mode:1;      /* relative addressing, hopefully! */
    GLuint pad0:1;
 

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 0bfbec9d1405f2b59dd80340af8653990e7f6352..460521615c6e3a3f1a23a9e3809adb31c9d5ff89 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -64,7 +64,7 @@ static void brw_set_dest( struct brw_instruction *insn,
 
       if (insn->header.access_mode == BRW_ALIGN_1) {
         insn->bits1.da1.dest_subreg_nr = dest.subnr;
-        insn->bits1.da1.dest_horiz_stride = BRW_HORIZONTAL_STRIDE_1;
+        insn->bits1.da1.dest_horiz_stride = dest.hstride;
       }
       else {
         insn->bits1.da16.dest_subreg_nr = dest.subnr / 16;
@@ -78,7 +78,7 @@ static void brw_set_dest( struct brw_instruction *insn,
        */
       if (insn->header.access_mode == BRW_ALIGN_1) {
         insn->bits1.ia1.dest_indirect_offset = dest.dw1.bits.indirect_offset;
-        insn->bits1.ia1.dest_horiz_stride = BRW_HORIZONTAL_STRIDE_1;
+        insn->bits1.ia1.dest_horiz_stride = dest.hstride;
       }
       else {
         insn->bits1.ia16.dest_indirect_offset = dest.dw1.bits.indirect_offset;