whoops, test of SV.bc in wrong place

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 5b548764db44f38b289c60c7fe01134008dc3ec9..96f9e71dce5b4246fd44f1db79cb6717a4eca260 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -777,6 +777,17 @@ class SVP64Asm:
             assert sv_mode is None, \
                 "LD shift cannot have modes (%s) applied" % sv_mode
 
+        # now create mode and (overridden) src/dst widths
+        # XXX TODO: sanity-check bc modes
+        if is_bc:
+            sv_mode = ((bc_svstep << SVP64MODE.MOD2_MSB) |
+                      (bc_vlset << SVP64MODE.MOD2_LSB) |
+                      (bc_snz << SVP64MODE.BC_SNZ))
+            srcwid = (bc_brc << 1) | bc_vsb
+            destwid = (bc_all << 1) | bc_lru
+
+        else:
+
             ######################################
             # "normal" mode
             if sv_mode is None:
@@ -855,15 +866,6 @@ class SVP64Asm:
                     assert rc_mode, "pr-mode BO only possible when Rc=1"
                     mode |= (predresult << SVP64MODE.BO_LSB) # set BO
 
-        # now create mode and (overridden) src/dst widths
-        # XXX TODO: sanity-check bc modes
-        if is_bc:
-            sv_mode = ((bc_svstep << SVP64MODE.MOD2_MSB) |
-                      (bc_vlset << SVP64MODE.MOD2_LSB) |
-                      (bc_snz << SVP64MODE.BC_SNZ))
-            srcwid = (bc_brc << 1) | bc_vsb
-            destwid = (bc_all << 1) | bc_lru
-
         # whewww.... modes all done :)
         # now put into svp64_rm
         mode |= sv_mode