update submodule

diff --git a/verilog/lm32/submodule b/verilog/lm32/submodule
index 584924363b77ecdfcc364697f954400f8649c9e6..dfd6ca7bfc1cf0a6ff306cb95bcae62915091301 160000 (submodule)
--- a/verilog/lm32/submodule
+++ b/verilog/lm32/submodule
@@ -1 +1 @@
-Subproject commit 584924363b77ecdfcc364697f954400f8649c9e6
+Subproject commit dfd6ca7bfc1cf0a6ff306cb95bcae62915091301