While free vendor toolchains are generally used by beginners or for prototyping
(situations where having a logic analyser in the design is generally very
-helpful) free toolchains are always provided without the proprietary logic
+helpful) free toolchains are always provided without the proprietary logic
analyzer solution... :(
Based on Migen, miscope aims to provide a free, portable and flexible
cores register mapping, importing miscope project gives you direct access to
all the cores!
-miscope produces.vcd output files to be analyzed in your favorite waveform viewer.
+miscope produces .vcd output files to be analyzed in your favorite waveform viewer.
[> Status:
Refactoring in progress...
from migen.bank import description, csrgen
from migen.bank.description import *
-from miscope import trigger, recorder, miIo, miLa
-
-import sys
-sys.path.append("../../")
-import spi2Csr
+from miscope import trigger, recorder, miio, mila
+from miscope.bridges import spi2csr
from timings import *
from constraints import Constraints
def get():
# migIo0
- miIo0 = miIo.MiIo(MIIO0_ADDR, 8, "IO")
+ miIo0 = miio.MiIo(MIIO0_ADDR, 8, "IO")
# migLa0
term0 = trigger.Term(trig0_width)
trigger0 = trigger.Trigger(trig0_width, [term0])
recorder0 = recorder.Recorder(dat0_width, record_size)
- miLa0 = miLa.MiLa(MILA0_ADDR, trigger0, recorder0)
+ miLa0 = mila.MiLa(MILA0_ADDR, trigger0, recorder0)
# migLa1
term1 = trigger.Term(trig1_width)
trigger1 = trigger.Trigger(trig1_width, [term1])
recorder1 = recorder.Recorder(dat1_width, record_size)
- miLa1 = miLa.MiLa(MILA1_ADDR, trigger1, recorder1)
+ miLa1 = mila.MiLa(MILA1_ADDR, trigger1, recorder1)
# Spi2Csr
- spi2csr0 = spi2Csr.Spi2Csr(16,8)
+ spi2csr0 = spi2csr.Spi2Csr(16,8)
# Csr Interconnect
csrcon0 = csr.Interconnect(spi2csr0.csr,
[
miIo0.bank.bus,
- miLa0.trig.bank.bus,
- miLa0.rec.bank.bus,
- miLa1.trig.bank.bus,
- miLa1.rec.bank.bus,
+ miLa0.trigger.bank.bus,
+ miLa0.recorder.bank.bus,
+ miLa1.trigger.bank.bus,
+ miLa1.recorder.bank.bus,
])
comb = []
# MigLa0 input
comb += [
- miLa0.in_trig.eq(sig_gen),
- miLa0.in_dat.eq(sig_gen)
+ miLa0.trig.eq(sig_gen),
+ miLa0.dat.eq(sig_gen)
]
# MigLa1 input
comb += [
- miLa1.in_trig[:8].eq(spi2csr0.csr.dat_w),
- miLa1.in_trig[8:24].eq(spi2csr0.csr.adr),
- miLa1.in_trig[24].eq(spi2csr0.csr.we),
- miLa1.in_dat[:8].eq(spi2csr0.csr.dat_w),
- miLa1.in_dat[8:24].eq(spi2csr0.csr.adr),
- miLa1.in_dat[24].eq(spi2csr0.csr.we)
+ miLa1.trig[:8].eq(spi2csr0.csr.dat_w),
+ miLa1.trig[8:24].eq(spi2csr0.csr.adr),
+ miLa1.trig[24].eq(spi2csr0.csr.we),
+ miLa1.dat[:8].eq(spi2csr0.csr.dat_w),
+ miLa1.dat[8:24].eq(spi2csr0.csr.adr),
+ miLa1.dat[24].eq(spi2csr0.csr.we)
]
from migen.bank import description, csrgen
from migen.bank.description import *
-from miscope import trigger, recorder, miIo, miLa
-
-import sys
-sys.path.append("../../")
-import spi2Csr
+from miscope import trigger, recorder, miio, mila
+from miscope.bridges import spi2csr
from timings import *
from constraints import Constraints
def get():
# migIo0
- miIo0 = miIo.MiIo(MIIO0_ADDR, 8, "IO")
+ miIo0 = miio.MiIo(MIIO0_ADDR, 8, "IO")
# migLa0
term0 = trigger.Term(trig0_width)
trigger0 = trigger.Trigger(trig0_width, [term0])
recorder0 = recorder.Recorder(dat0_width, record_size)
- miLa0 = miLa.MiLa(MILA0_ADDR, trigger0, recorder0)
+ miLa0 = mila.MiLa(MILA0_ADDR, trigger0, recorder0)
# migLa1
term1 = trigger.Term(trig1_width)
trigger1 = trigger.Trigger(trig1_width, [term1])
recorder1 = recorder.Recorder(dat1_width, record_size)
- miLa1 = miLa.MiLa(MILA1_ADDR, trigger1, recorder1)
+ miLa1 = mila.MiLa(MILA1_ADDR, trigger1, recorder1)
# Spi2Csr
- spi2csr0 = spi2Csr.Spi2Csr(16,8)
+ spi2csr0 = spi2csr.Spi2Csr(16,8)
# Csr Interconnect
csrcon0 = csr.Interconnect(spi2csr0.csr,
[
miIo0.bank.bus,
- miLa0.trig.bank.bus,
- miLa0.rec.bank.bus,
- miLa1.trig.bank.bus,
- miLa1.rec.bank.bus,
+ miLa0.trigger.bank.bus,
+ miLa0.recorder.bank.bus,
+ miLa1.trigger.bank.bus,
+ miLa1.recorder.bank.bus,
])
comb = []
# MigLa0 input
comb += [
- miLa0.in_trig.eq(sig_gen),
- miLa0.in_dat.eq(sig_gen)
+ miLa0.trig.eq(sig_gen),
+ miLa0.dat.eq(sig_gen)
]
# MigLa1 input
comb += [
- miLa1.in_trig[:8].eq(spi2csr0.csr.dat_w),
- miLa1.in_trig[8:24].eq(spi2csr0.csr.adr),
- miLa1.in_trig[24].eq(spi2csr0.csr.we),
- miLa1.in_dat[:8].eq(spi2csr0.csr.dat_w),
- miLa1.in_dat[8:24].eq(spi2csr0.csr.adr),
- miLa1.in_dat[24].eq(spi2csr0.csr.we)
+ miLa1.trig[:8].eq(spi2csr0.csr.dat_w),
+ miLa1.trig[8:24].eq(spi2csr0.csr.adr),
+ miLa1.trig[24].eq(spi2csr0.csr.we),
+ miLa1.dat[:8].eq(spi2csr0.csr.dat_w),
+ miLa1.dat[8:24].eq(spi2csr0.csr.adr),
+ miLa1.dat[24].eq(spi2csr0.csr.we)
]
self.set_address(address)
self.set_interface(interface)
- def set_interface(self, i):
- self.interface = i
- self.trigger.set_interface(i)
- self.recorder.set_interface(i)
+ def set_interface(self, interface):
+ self.interface = interface
+ self.trigger.set_interface(interface)
+ self.recorder.set_interface(interface)
- def set_address(self, i):
+ def set_address(self, address):
self.address = address
self.trigger.set_address(self.address)
self.recorder.set_address(self.address + 0x0200)
from migen.bank import description, csrgen
from migen.bank.description import *
from migen.corelogic.misc import optree
+from migen.corelogic.fsm import *
class Storage:
#
def get_fragment(self):
comb = [
self._push_port.adr.eq(self._push_ptr),
- self._push_port.we.eq(self.push),
+ self._push_port.we.eq(self.push_stb),
self._push_port.dat_w.eq(self.push_dat),
self._pull_port.adr.eq(self._pull_ptr),
# Idle
fsm.act(fsm.IDLE,
If(self.start,
- fsm.next_state(fsm.PUSH),
+ fsm.next_state(fsm.ACTIVE),
active_rising.eq(1)
),
idle_ongoing.eq(1)
active_ongoing.eq(1)
)
- sync +=[
+ sync =[
If(active_rising,
self._push_ptr_stop.eq(self._push_ptr + self.size - self.offset),
self._pull_ptr.eq(self._push_ptr-self.offset-1)
),
If(self.push_stb, self._push_ptr.eq(self._push_ptr+1)),
]
- comb +=[self.done.eq((self._put_ptr == self._put_ptr_stop) & active_ongoing)]
+ comb +=[self.done.eq((self._push_ptr == self._push_ptr_stop) & active_ongoing)]
- return Fragment(comb, sync, memories=self._mem)
+ return Fragment(comb, sync, memories=[self._mem])
class Sequencer:
#
def get_fragment(self):
- idle_rising = Signal()
+ idle_rising = Signal()
idle_ongoing = Signal()
active_rising = Signal()
active_ongoing = Signal()
# Idle
fsm.act(fsm.IDLE,
If(self.ctl_arm,
- fsm.next_state(fsm.PUSH),
+ fsm.next_state(fsm.ACTIVE),
active_rising.eq(1)
),
idle_ongoing.eq(1)
# Active
fsm.act(fsm.ACTIVE,
- If(self.rec_done | self.rst,
+ If(self.rec_done,
fsm.next_state(fsm.IDLE),
idle_rising.eq(1)
),
active_ongoing.eq(1)
)
- comb +=[self.enable.eq(active_ongoing)]
+ comb =[self.enable.eq(active_ongoing)]
# trig_hit rising_edge
_hit_d = Signal()
_hit_rising = Signal()
- sync +=[_hit_d.eq(self.hit)]
- comb +=[_hit_rising.eq(self.hit & ~_hit_d]
+ sync =[_hit_d.eq(self.hit)]
+ comb +=[_hit_rising.eq(self.hit & ~_hit_d)]
# connexion
comb = [
access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self.regs = [self._rst, self._arm, self._done, self._size, self._offset,
- self._get, self._get_dat]
+ self._pull_stb, self._pull_dat]
self.bank = csrgen.Bank(self.regs, address=address)
def set_interface(self, interface):
self.interface = interface
- def get_fragment(self):
- _pull_d = Signal()
- _pull_rising = Signal()
+ def get_fragment(self):
+ _pull_stb_d = Signal()
+ _pull_stb_rising = Signal()
sync = [
- _pull_d.eq(self._pull.field.r),
- _pull_rising.eq(self._pull.field.r & ~_pull_d)
+ _pull_stb_d.eq(self._pull_stb.field.r),
+ _pull_stb_rising.eq(self._pull_stb.field.r & ~_pull_stb_d)
]
# Bank <--> Storage / Sequencer
self._done.field.w.eq(self.sequencer.ctl_done),
- self.storage.pull_stb.eq(_pull_rising),
+ self.storage.pull_stb.eq(_pull_stb_rising),
self._pull_dat.field.w.eq(self.storage.pull_dat)
]
self.sequencer.rec_done.eq(self.storage.done),
self.sequencer.hit.eq(self.hit),
- self.storage.put_stb.eq(self.sequencer.enable),
- self.storage.put_dat.eq(self.dat)
+ self.storage.push_stb.eq(self.sequencer.enable),
+ self.storage.push_dat.eq(self.dat)
]
return self.bank.get_fragment() + Fragment(comb, sync) +\
self.o = Signal()
self.reg_p = RegParams("term_reg", 0, width, 2)
+ self.reg = None
- def get_registers(self, reg):
- comb = [self.t.eq(reg.field.r[0*self.width:1*self.width])]
- comb += [self.m.eq(reg.field.r[1*self.width:2*self.width])]
+ def get_registers(self):
+ comb = [self.t.eq(self.reg.field.r[0*self.width:1*self.width])]
+ comb += [self.m.eq(self.reg.field.r[1*self.width:2*self.width])]
return comb
- def get_fragment(self, reg):
+ def get_fragment(self):
comb = [self.o.eq((self.m & self.i) == self.t)]
- comb += self.get_registers(reg)
+ comb += self.get_registers()
return Fragment(comb)
#
self.interface = None
self.reg_p = RegParams("range_reg", 0, width, 2)
+ self.reg = None
self.i = Signal(width)
self.low = Signal(width)
self.high = Signal(width)
self.o = Signal()
- def get_registers(self, reg):
- comb = [self.low.eq(reg.field.r[0*self.width:1*self.width])]
- comb += [self.low.eq(reg.field.r[1*self.width:2*self.width])]
+ def get_registers(self):
+ comb = [self.low.eq(self.reg.field.r[0*self.width:1*self.width])]
+ comb += [self.low.eq(self.reg.field.r[1*self.width:2*self.width])]
return comb
- def get_fragment(self, reg):
+ def get_fragment(self):
comb = [self.o.eq((self.i >= self.low) & (self.i <= self.high))]
- comb += self.get_registers(reg)
+ comb += self.get_registers()
return Fragment(comb)
#
# Driver
self.mode = mode
self.interface = None
- self.reg_p = RegParams("edge_reg", 0, width, len(self.mode)
+ self.reg_p = RegParams("edge_reg", 0, width, len(self.mode))
+ self.reg = None
self.i = Signal(self.width)
self.i_d = Signal(self.width)
self.bo = Signal()
self.o = Signal()
- def get_registers(self, reg):
+ def get_registers(self):
comb = []
i = 0
if "R" in self.mode:
- comb += [self.r_mask.eq(reg.field.r[i*self.width:(i+1)*self.width])]
+ comb += [self.r_mask.eq(self.reg.field.r[i*self.width:(i+1)*self.width])]
i += 1
if "F" in self.mode:
- comb += [self.f_mask.eq(reg.field.r[i*self.width:(i+1)*self.width])]
+ comb += [self.f_mask.eq(self.reg.field.r[i*self.width:(i+1)*self.width])]
i += 1
if "B" in self.mode:
- comb += [self.b_mask.eq(reg.field.r[i*self.width:(i+1)*self.width])]
+ comb += [self.b_mask.eq(self.reg.field.r[i*self.width:(i+1)*self.width])]
i += 1
return comb
- def get_fragment(self, reg):
+ def get_fragment(self):
comb = []
sync = [self.i_d.eq(self.i)]
comb += [self.o.eq(self.ro | self.fo | self.bo)]
# Registers
- comb += self.get_registers(reg)
+ comb += self.get_registers()
return Fragment(comb, sync)
self.o = Signal()
self.reg_p = RegParams("sum_reg", 0, 8, 4)
+ self.reg = None
self.prog_stb = Signal()
self.prog_adr = Signal(width)
self._lut_port = self._mem.get_port()
self._prog_port = self._mem.get_port(write_capable=True)
- def get_registers(self, reg):
+ def get_registers(self):
comb = [
- self.prog_adr.eq(reg.field.r[0:16]),
- self.prog_dat.eq(reg.field.r[16]),
- self.prog_stb.eq(reg.field.r[17])
+ self.prog_adr.eq(self.reg.field.r[0:16]),
+ self.prog_dat.eq(self.reg.field.r[16]),
+ self.prog_stb.eq(self.reg.field.r[17])
]
return comb
- def get_fragment(self, reg):
+ def get_fragment(self):
comb = [
self._lut_port.adr.eq(self.i),
self._o.eq(self._lut_port.dat_r),
self._prog_port.adr.eq(self.prog_adr),
self._prog_port.we.eq(self.prog_stb),
- self._prog_port.dat_w.eq(self.prog_dat)
+ self._prog_port.dat_w.eq(self.prog_dat),
self.o.eq(self._o)
]
- comb += get_registers(reg)
- return Fragment(comb, sync, memories=self._mem)
+ comb += self.get_registers()
+ return Fragment(comb, memories=[self._mem])
#
#Driver
for port in self.ports:
rf = RegisterField(port.reg_p.name, port.reg_p.size, reset=0,
access_bus=WRITE_ONLY, access_dev=READ_ONLY)
- setattr(self, port.reg_name, rf)
+ setattr(self, port.reg_p.name, rf)
# generate sum csr registers fields
self.sum_reg = RegisterField(self.sum.reg_p.name, self.sum.reg_p.size, reset=0,
self.bank = csrgen.Bank(self.regs, address=address)
# update base addr & interface
- self.set_address(self.address)
- self.set_interface(self.interface)
+ self.set_address(address)
+ self.set_interface(interface)
+ self.set_registers()
def set_address(self, address):
self.address = address
for port in self.ports:
port.interface = self.interface
self.sum.interface = self.interface
+
+ def set_registers(self):
+ self.sum.reg=self.sum_reg
+ for port in self.ports:
+ port.reg=getattr(self, port.reg_p.name)
def get_fragment(self):
# connect trig to input of each trig element
- comb = [port.i.eq(self.in_trig) for port in self.ports]
+ comb = [port.i.eq(self.trig) for port in self.ports]
# connect output of trig elements to sum
comb += [self.sum.i[j].eq(self.ports[j].o) for j in range(len(self.ports))]
comb += [self.hit.eq(self.sum.o)]
# add ports & sum to frag
- frag = self.bank.get_fragment()
- frag += self.sum.get_fragment(self.sum_reg)
+ frag = self.bank.get_fragment()
+ frag += self.sum.get_fragment()
for port in self.ports:
- frag += port.get_fragment(getattr(self, port.reg_name))
+ frag += port.get_fragment()
return frag + Fragment(comb)
projects / litex.git / commitdiff