Zero out ports

diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg
index 2fc943a66b2e047e9a32e5149255af653a9906c8..d4b4b8e221043b47c1c2e75395ee681d347f967b 100644 (file)
--- a/passes/pmgen/xilinx_dsp_cascade.pmg
+++ b/passes/pmgen/xilinx_dsp_cascade.pmg
@@ -67,7 +67,7 @@ finally
                                        Wire *cascade = module->addWire(NEW_ID, 30);
                                        dsp_pcin->setPort(ID(ACIN), cascade);
                                        dsp->setPort(ID(ACOUT), cascade);
-                                       dsp_pcin->unsetPort(ID(A));
+                                       dsp_pcin->setPort(ID(A), Const(0, 30));
                                        add_siguser(cascade, dsp_pcin);
                                        add_siguser(cascade, dsp);
 
@@ -80,7 +80,7 @@ finally
                                        Wire *cascade = module->addWire(NEW_ID, 18);
                                        dsp_pcin->setPort(ID(BCIN), cascade);
                                        dsp->setPort(ID(BCOUT), cascade);
-                                       dsp_pcin->unsetPort(ID(B));
+                                       dsp_pcin->setPort(ID(B), Const(0, 18));
                                        add_siguser(cascade, dsp_pcin);
                                        add_siguser(cascade, dsp);