sram: fix sub-word write

diff --git a/milkymist/sram/__init__.py b/milkymist/sram/__init__.py
index 792ae1525cb0bc86b8d56e5e8fd2b1bdfb3f5ca2..d30bf87ffd3f1c82ca669dbc1db072c81fc77a4c 100644 (file)
--- a/milkymist/sram/__init__.py
+++ b/milkymist/sram/__init__.py
@@ -9,7 +9,7 @@ class SRAM:
        def get_fragment(self):
                # generate write enable signal
                we = Signal(BV(4))
-               comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.we_i & self.bus.sel_i[3-i])
+               comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.we_i & self.bus.sel_i[i])
                        for i in range(4)]
                # split address
                nbits = bits_for(self.depth-1)

diff --git a/top.py b/top.py
index 7014158efc82222adc67654eb6de530ed6e88fd6..8d2bb1f96291080099d781cba3b9da7bbf0446b8 100644 (file)
--- a/top.py
+++ b/top.py
@@ -8,7 +8,7 @@ import constraints
 def get():
        MHz = 1000000
        clk_freq = 80*MHz
-       sram_size = 4096 # in kilobytes
+       sram_size = 4096 # in bytes
        
        clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
        reset0 = m1reset.M1Reset()