Add clk2fflogic memory support

diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index fbd71fe58bed67d4c9e8468073a1621312b854e4..d334cf7d99130e39aa6c6ab5a2e378ea158c6831 100644 (file)
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -74,7 +74,83 @@ struct Clk2fflogicPass : public Pass {
                        {
                                if (cell->type.in("$mem"))
                                {
-                                       log_error("Currently there is no support for memories in clk2fflogic. Run memory_map first to convert memories to logic.\n");
+                                       int abits = cell->getParam("\\ABITS").as_int();
+                                       int width = cell->getParam("\\WIDTH").as_int();
+                                       int rd_ports = cell->getParam("\\RD_PORTS").as_int();
+                                       int wr_ports = cell->getParam("\\WR_PORTS").as_int();
+
+                                       for (int i = 0; i < rd_ports; i++) {
+                                               if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool())
+                                                       log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! "
+                                                                       "Call \"memory\" with -nordff to avoid this error.\n", i, log_id(cell), log_id(module));
+                                       }
+
+                                       Const wr_clk_en_param = cell->getParam("\\WR_CLK_ENABLE");
+                                       Const wr_clk_pol_param = cell->getParam("\\WR_CLK_POLARITY");
+
+                                       SigSpec wr_clk_port = cell->getPort("\\WR_CLK");
+                                       SigSpec wr_en_port = cell->getPort("\\WR_EN");
+                                       SigSpec wr_addr_port = cell->getPort("\\WR_ADDR");
+                                       SigSpec wr_data_port = cell->getPort("\\WR_DATA");
+
+                                       for (int wport = 0; wport < wr_ports; wport++)
+                                       {
+                                               bool clken = wr_clk_en_param[wport] == State::S1;
+                                               bool clkpol = wr_clk_pol_param[wport] == State::S1;
+
+                                               if (!clken)
+                                                       continue;
+
+                                               SigBit clk = wr_clk_port[wport];
+                                               SigSpec en = wr_en_port.extract(wport*width, width);
+                                               SigSpec addr = wr_addr_port.extract(wport*abits, abits);
+                                               SigSpec data = wr_data_port.extract(wport*width, width);
+
+                                               log("Modifying write port %d on memory %s.%s: CLK=%s, A=%s, D=%s\n",
+                                                               wport, log_id(module), log_id(cell), log_signal(clk),
+                                                               log_signal(addr), log_signal(data));
+
+                                               Wire *past_clk = module->addWire(NEW_ID);
+                                               past_clk->attributes["\\init"] = clkpol ? State::S1 : State::S0;
+                                               module->addFf(NEW_ID, clk, past_clk);
+
+                                               SigSpec clock_edge_pattern;
+
+                                               if (clkpol) {
+                                                       clock_edge_pattern.append_bit(State::S0);
+                                                       clock_edge_pattern.append_bit(State::S1);
+                                               } else {
+                                                       clock_edge_pattern.append_bit(State::S1);
+                                                       clock_edge_pattern.append_bit(State::S0);
+                                               }
+
+                                               SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern);
+
+                                               SigSpec en_q = module->addWire(NEW_ID, GetSize(addr));
+                                               module->addFf(NEW_ID, en, en_q);
+
+                                               SigSpec addr_q = module->addWire(NEW_ID, GetSize(addr));
+                                               module->addFf(NEW_ID, addr, addr_q);
+
+                                               SigSpec data_q = module->addWire(NEW_ID, GetSize(data));
+                                               module->addFf(NEW_ID, data, data_q);
+
+                                               wr_clk_port[wport] = State::S0;
+                                               wr_en_port.replace(wport*width, module->Mux(NEW_ID, Const(0, GetSize(en_q)), en_q, clock_edge));
+                                               wr_addr_port.replace(wport*abits, addr_q);
+                                               wr_data_port.replace(wport*width, data_q);
+
+                                               wr_clk_en_param[wport] = State::S0;
+                                               wr_clk_pol_param[wport] = State::S0;
+                                       }
+
+                                       cell->setParam("\\WR_CLK_ENABLE", wr_clk_en_param);
+                                       cell->setParam("\\WR_CLK_POLARITY", wr_clk_pol_param);
+
+                                       cell->setPort("\\WR_CLK", wr_clk_port);
+                                       cell->setPort("\\WR_EN", wr_en_port);
+                                       cell->setPort("\\WR_ADDR", wr_addr_port);
+                                       cell->setPort("\\WR_DATA", wr_data_port);
                                }
 
                                if (cell->type.in("$dlatch"))