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diff --git a/openpower/sv/rfc/ls005.mdwn b/openpower/sv/rfc/ls005.mdwn
index c4e817202896f0c3e8e014838ff3829f5e5506e3..b2981600caa9a38c99143dc9e8b5d2dd6f5ddc8a 100644 (file)
--- a/openpower/sv/rfc/ls005.mdwn
+++ b/openpower/sv/rfc/ls005.mdwn
@@ -205,6 +205,29 @@ Therefore a little more thought is required. Should this simply be UNDEFINED
 behaviour when XLEN=8/16 and L=1? When XLEN=16, L=0 the instruction is still
 valid. Would it be costly at the Decoder?
 
+## Trap Word Immediate
+
+Like FP Single operations there also exist operations at "half of regfile width"
+in the Integer realm.  They are discernable with the designation `Word` in their
+title.
+
+```
+    a <- EXTS((RA)[XLEN/2:XLEN-1])
+    if (a < EXTS(SI)) & TO[0]  then TRAP
+    if (a > EXTS(SI)) & TO[1]  then TRAP
+    if (a = EXTS(SI)) & TO[2]  then TRAP
+    if (a <u EXTS(SI)) & TO[3] then TRAP
+    if (a >u EXTS(SI)) & TO[4] then TRAP
+```
+
+Here, EXTS receives **half** of the bits of its input register operand, RA.
+Note this is **not** "32 bit because a Word is 32-bit". The definition
+"Trap Word Immediate" has to be replaced with "Trap Half-register-width Immediate"
+but this is very clumsy.
+
+When XLEN=8 "half register width" is clearly 4 bit, thus the LSB nibble is tested,
+but still sign-extended for comparison
+against the 16-bit signed immediate.
 
 \newpage{}