ac/surface: increment surf_index only when tile swizzle is allowed

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 61b4e41a3baced51b54f2fd0dbc41d738aa13f85..68700f4102403997fc1662271719262579e84b11 100644 (file)
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -30,6 +30,7 @@
 #include "amdgpu_id.h"
 #include "ac_gpu_info.h"
 #include "util/macros.h"
+#include "util/u_atomic.h"
 #include "util/u_math.h"
 
 #include <errno.h>
@@ -706,13 +707,14 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
        surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
 
        /* Work out tile swizzle. */
-       if (surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
+       if (config->info.surf_index &&
+           surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
            !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
            (config->info.samples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) {
                ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
                ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
 
-               AddrBaseSwizzleIn.surfIndex = config->info.surf_index;
+               AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
                AddrBaseSwizzleIn.tileIndex = AddrSurfInfoIn.tileIndex;
                AddrBaseSwizzleIn.macroModeIndex = AddrSurfInfoOut.macroModeIndex;
                AddrBaseSwizzleIn.pTileInfo = AddrSurfInfoOut.pTileInfo;

diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 01a71f32b2f6df92c0ac807a378262a541e8cc2d..b2620f95055c4bf5847f6284890e0319834b97a1 100644 (file)
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -209,10 +209,10 @@ struct ac_surf_info {
        uint32_t width;
        uint32_t height;
        uint32_t depth;
-       uint32_t surf_index;
        uint8_t samples;
        uint8_t levels;
        uint16_t array_size;
+       uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
 };
 
 struct ac_surf_config {

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 499287d459bdf895b919096153f09e30b4c5d1d7..8456d3ab1f6c2c92bf56732b1b540507b3755f43 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -809,7 +809,7 @@ radv_image_create(VkDevice _device,
        image->shareable = vk_find_struct_const(pCreateInfo->pNext,
                                                EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
        if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
-               image->info.surf_index = p_atomic_inc_return(&device->image_mrt_offset_counter) - 1;
+               image->info.surf_index = &device->image_mrt_offset_counter;
        }
 
        radv_init_surface(device, &image->surface, create_info);

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 1a2b7c4afb3adccf3776e652d709442e594be185..d438b6d662b35c79210b3bbdf8ff015dec6207ff 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -92,6 +92,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
    config.info.levels = tex->last_level + 1;
    config.is_3d = !!(tex->target == PIPE_TEXTURE_3D);
    config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE);
+   config.info.surf_index = NULL;
 
    return ac_compute_surface(ws->addrlib, &ws->info, &config, mode, surf);
 }