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i965/gen6+: Invalidate constant cache on brw_emit_mi_flush().
authorFrancisco Jerez <currojerez@riseup.net>
Fri, 9 Dec 2016 02:00:17 +0000 (18:00 -0800)
committerFrancisco Jerez <currojerez@riseup.net>
Thu, 15 Dec 2016 00:50:26 +0000 (16:50 -0800)
In order to make sure that the constant cache is coherent with
previous rendering when we start using it for pull constant loads.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/brw_pipe_control.c patch | blob | history

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index dd426bf2154ec8249817715d209a6e78462362a1..b8f740640f25384dbe13e0d9789b5104b842da02 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -351,6 +351,7 @@ brw_emit_mi_flush(struct brw_context *brw)
       int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
       if (brw->gen >= 6) {
          flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
+                  PIPE_CONTROL_CONST_CACHE_INVALIDATE |
                   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
                   PIPE_CONTROL_VF_CACHE_INVALIDATE |
                   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |