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diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index f8a7a4a18db3331081bdbd7f6a7d62e6cdebad2d..f224e0902ec0b87dec3308fbd0ba4bc62cd57c67 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -71,16 +71,13 @@ SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:
 
 | 4 | 5 | 19-20 |  21 | 22   23 |  description     |
 | - | - | ----- | --- |---------|----------------- |
-|sz |SNZ| 00    |   0 |  dz  /  | normal mode                      |
-|sz |SNZ| 00    |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
-|sz |SNZ| 00    |   1 | 1   /   | parallel reduce mode (mapreduce), SUBVL=1 |
-|sz |SNZ| 00    |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
-|sz |SNZ| 01/10 | inv |  CR-bit | Ffirst 3-bit mode      |
-|sz |SNZ| 01/10 | inv |  dz /   | Ffirst 5-bit mode       |
-|sz |SNZ| 11    | rsv | rsvd    | reserved |
-
-`VLI=0` when bits 19-20=0b01. 
-`VLI=1` when bits 19-20=0b10. 
+|sz |SNZ| 0 0   |   0 |  dz  /  | normal mode                      |
+|sz |SNZ| 0 0   |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
+|sz |SNZ| 0 0   |   1 | 1   /   | parallel reduce mode (mapreduce), SUBVL=1 |
+|sz |SNZ| 0 0   |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
+|sz |SNZ| 0 1   | rsv | rsvd    | reserved |
+|sz |SNZ| 1 VLI | inv |  CR-bit | Ffirst 3-bit mode      |
+|sz |SNZ| 1 VLI | inv |  dz /   | Ffirst 5-bit mode       |
 
 Fields: