Fixed building verific bindings

diff --git a/frontends/verific/build_amd64.txt b/frontends/verific/build_amd64.txt
index 2f325e515d3a6fab23432c21a9975771c833f24c..2c3ba7b4d21a868465d7da3e9f079b200a2147be 100644 (file)
--- a/frontends/verific/build_amd64.txt
+++ b/frontends/verific/build_amd64.txt
@@ -6,7 +6,7 @@ only have the i386 eval version of Verific:
 1.) Use a Makefile.conf like the following one:
 
 --snip--
-CONFIG := clang-debug
+CONFIG := clang
 ENABLE_TCL := 0
 ENABLE_QT4 := 0
 ENABLE_ABC := 0

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 30f452181b637e44006f13c780414db8d833de43..1ffcc4229a3bfb801b8699b03f240bfb34fc40ec 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -687,7 +687,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
                        RTLIL::SigSpec data = operatorOutput(inst, net_map, module);
 
                        RTLIL::Cell *cell = module->addCell(RTLIL::escape_id(inst->Name()), "$memrd");
-                       cell->parameters["\\MEMID"] = memory->name;
+                       cell->parameters["\\MEMID"] = memory->name.str();
                        cell->parameters["\\CLK_ENABLE"] = false;
                        cell->parameters["\\CLK_POLARITY"] = true;
                        cell->parameters["\\TRANSPARENT"] = false;
@@ -709,7 +709,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
                        RTLIL::SigSpec data = operatorInput2(inst, net_map);
 
                        RTLIL::Cell *cell = module->addCell(RTLIL::escape_id(inst->Name()), "$memwr");
-                       cell->parameters["\\MEMID"] = memory->name;
+                       cell->parameters["\\MEMID"] = memory->name.str();
                        cell->parameters["\\CLK_ENABLE"] = false;
                        cell->parameters["\\CLK_POLARITY"] = true;
                        cell->parameters["\\PRIORITY"] = 0;