* Other interests: Nearly anything that floats, flies, or has an engine with wheels
## [[Andrey Miroshnikov|andreym]]
-* Languages: C, Python, Verilog
+* Languages: C, Python, Verilog, Shell script
* Interests: Analogue/digital electronics, RF, mobile comms, compilers, FPGAs, discrete mathematics, microarchitecture, Unix OSs, PCB design
* Experience: FPGA/ASIC system validation, instrument automation using VISA, PCB design (KiCAD, Altium)
-* Other interests: Lingua Latina, Philosophy, History
+* Other interests: King James Bible, Russian Synodal Bible, Languages, Philosophy, History
* Availability: Full-time
* IRC: octavius
- (Pinout) - NGI POINTER Gigabit Router Pinout Considerations
* <https://bugs.libre-soc.org/show_bug.cgi?id=50> Working on pinmux with Luke
- nmigen pinmux
-* <https://bugs.libre-soc.org/show_bug.cgi?id=762> Peripheral Pin Muxing Development
- - Bug for the pinmux and GPIO block development
-* <https://bugs.libre-soc.org/show_bug.cgi?id=764> Documentation of I/O Core/Pad JTAG Tests
- - Documentation of the development and tests from bugs #763 and #762
+* <https://bugs.libre-soc.org/show_bug.cgi?id=846> Pinmux Pinspec Interconnect Auto-Generation
## On hold
* Looking at Wishbone B4 and AXI specifications for streaming extension.
## Submitted to NLNet but not yet paid
-* Nothing yet
+### NLnet.2019.02
+
+* [Bug #762](https://bugs.libre-soc.org/show_bug.cgi?id=762):
+ Peripheral Pin Muxing Development
+ * €1500 out of total of €1800
+
+* [Bug #764](https://bugs.libre-soc.org/show_bug.cgi?id=764):
+ Documentation of I/O Core/Pad JTAG Tests
+ * €1500 which is the total amount
## Paid by NLNet