# address mapping in the case of a DRAM
for r in system.mem_ranges:
for i in xrange(nbr_mem_ctrls):
- mem_ctrls.append(create_mem_ctrl(cls, r, i, nbr_mem_ctrls,
- intlv_bits,
- system.cache_line_size.value))
+ mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
+ system.cache_line_size.value)
+ # Set the number of ranks based on the command-line
+ # options if it was explicitly set
+ if issubclass(cls, m5.objects.DRAMCtrl) and \
+ options.mem_ranks:
+ mem_ctrl.ranks_per_channel = options.mem_ranks
+
+ mem_ctrls.append(mem_ctrl)
system.mem_ctrls = mem_ctrls
help = "type of memory to use")
parser.add_option("--mem-channels", type="int", default=1,
help = "number of memory channels")
+ parser.add_option("--mem-ranks", type="int", default=None,
+ help = "number of memory ranks per channel")
parser.add_option("--mem-size", action="store", type="string",
default="512MB",
help="Specify the physical memory size (single memory)")
busBusyUntil(0), prevArrival(0),
nextReqTime(0), activeRank(0), timeStampOffset(0)
{
+ // sanity check the ranks since we rely on bit slicing for the
+ // address decoding
+ fatal_if(!isPowerOf2(ranksPerChannel), "DRAM rank count of %d is not "
+ "allowed, must be a power of two\n", ranksPerChannel);
+
for (int i = 0; i < ranksPerChannel; i++) {
Rank* rank = new Rank(*this, p);
ranks.push_back(rank);