gas/

2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>

	* NEWS: Mention XSAVE.  Change CLMUL to PCLMUL.

	* config/tc-i386.c (cpu_arch): Add .pclmul.
	(md_show_usage): Replace clmul with pclmul.
	* doc/c-i386.texi: Likewise.

gas/testsuite/

2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/arch-10.s: Likewise.
	* gas/i386/clmul-intel.d: Likewise.
	* gas/i386/clmul.d: Likewise.
	* gas/i386/clmul.s: Likewise.
	* gas/i386/x86-64-arch-2.s: Likewise.
	* gas/i386/x86-64-clmul-intel.d: Likewise.
	* gas/i386/x86-64-clmul.d: Likewise.
	* gas/i386/x86-64-clmul.s: Likewise.

	* gas/i386/arch-10.d: Replace clmul with pclmul.
	* gas/i386/x86-64-arch-2.d: Likewise.

opcodes/

2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
	with CPU_PCLMUL_FLAGS/CpuPCLMUL.
	(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
	* i386-opc.tbl: Likewise.

	* i386-opc.h (CpuCLMUL): Renamed to ...
	(CpuPCLMUL): This.
	(CpuFMA): Updated.
	(i386_cpu_flags): Replace cpuclmul with cpupclmul.

	* i386-init.h: Regenerated.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index fae8cb0de5fa6e16295ce6f07c460d12e4b7907e..43945ccb85bfe8a477db7fa913769872f835c4ba 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * NEWS: Mention XSAVE.  Change CLMUL to PCLMUL.
+
+       * config/tc-i386.c (cpu_arch): Add .pclmul.
+       (md_show_usage): Replace clmul with pclmul.
+       * doc/c-i386.texi: Likewise.
+
 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 
        * NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.

diff --git a/gas/NEWS b/gas/NEWS
index ce3cda139934dc316698caa5d622830694cf3a41..20ac4bba20c36019b6c0ccb800d6ac5f3ec0921b 100644 (file)
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -2,7 +2,7 @@
 * New command line option -msse2avx for x86 target to encode SSE
   instructions with VEX prefix.
 
-* Add Intel AES, CLMUL, AVX/FMA support for x86 target.
+* Add Intel XSAVE, AES, PCLMUL, AVX/FMA support for x86 target.
 
 * New command line options, -march=CPU[,+EXTENSION...], -mtune=CPU,
   -mmnemonic=[att|intel], -msyntax=[att|intel], -mindex-reg,

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index e8e8031811d7f1bda34cc3fd82be54fefb9846cf..4426697003ce9b4bd120d2c0d3bc36b5121f03af 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -647,8 +647,10 @@ static const arch_entry cpu_arch[] =
     CPU_XSAVE_FLAGS },
   { ".aes", PROCESSOR_UNKNOWN,
     CPU_AES_FLAGS },
+  { ".pclmul", PROCESSOR_UNKNOWN,
+    CPU_PCLMUL_FLAGS },
   { ".clmul", PROCESSOR_UNKNOWN,
-    CPU_CLMUL_FLAGS },
+    CPU_PCLMUL_FLAGS },
   { ".fma", PROCESSOR_UNKNOWN,
     CPU_FMA_FLAGS },
   { ".3dnow", PROCESSOR_UNKNOWN,
@@ -8045,7 +8047,7 @@ md_show_usage (stream)
                            generic32, generic64\n\
                           EXTENSION is combination of:\n\
                            mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
-                           avx, vmx, smx, xsave, aes, clmul, fma, 3dnow,\n\
+                           avx, vmx, smx, xsave, aes, pclmul, fma, 3dnow,\n\
                           3dnowa, sse4a, sse5, svme, abm, padlock\n"));
   fprintf (stream, _("\
   -mtune=CPU              optimize for CPU, CPU is one of:\n\

diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 105330e6b949a12e65edafaf9e09c07a317f2613..3e148a2571bb374a46bb9fb7c9b34ed8dba61043 100644 (file)
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -125,7 +125,7 @@ accept various extension mnemonics.  For example,
 @code{smx},
 @code{xsave},
 @code{aes},
-@code{clmul},
+@code{pclmul},
 @code{fma},
 @code{3dnow},
 @code{3dnowa},
@@ -832,7 +832,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave}
-@item @samp{.aes} @tab @samp{.clmul} @tab @samp{.fma}
+@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma}
 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
 @item @samp{.svme} @tab @samp{.abm}
 @item @samp{.padlock}

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index d7e72ebbc27c638308ff66be725cd6db01bb6076..dcb467e656534d344190e29a807d363f8a5e2526 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,21 @@
+2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL.
+       * gas/i386/arch-10-2.l: Likewise.
+       * gas/i386/arch-10-3.l: Likewise.
+       * gas/i386/arch-10-4.l: Likewise.
+       * gas/i386/arch-10.s: Likewise.
+       * gas/i386/clmul-intel.d: Likewise.
+       * gas/i386/clmul.d: Likewise.
+       * gas/i386/clmul.s: Likewise.
+       * gas/i386/x86-64-arch-2.s: Likewise.
+       * gas/i386/x86-64-clmul-intel.d: Likewise.
+       * gas/i386/x86-64-clmul.d: Likewise.
+       * gas/i386/x86-64-clmul.s: Likewise.
+
+       * gas/i386/arch-10.d: Replace clmul with pclmul.
+       * gas/i386/x86-64-arch-2.d: Likewise.
+
 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 
        * gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,

diff --git a/gas/testsuite/gas/i386/arch-10-1.l b/gas/testsuite/gas/i386/arch-10-1.l
index af717c4a87cd6422e5581e5d0046436ddd71d2c7..325e827b0b1db2eb17118ffa702cbb45b2309d39 100644 (file)
--- a/gas/testsuite/gas/i386/arch-10-1.l
+++ b/gas/testsuite/gas/i386/arch-10-1.l
@@ -53,7 +53,7 @@ GAS LISTING .*
 [      ]*26[   ]+xgetbv
 [      ]*27[   ]+\# AES
 [      ]*28[   ]+aesenc  \(%ecx\),%xmm0
-[      ]*29[   ]+\# CLMUL
+[      ]*29[   ]+\# PCLMUL
 [      ]*30[   ]+pclmulqdq \$8,%xmm1,%xmm0
 [      ]*31[   ]+\# FMA
 [      ]*32[   ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7

diff --git a/gas/testsuite/gas/i386/arch-10-2.l b/gas/testsuite/gas/i386/arch-10-2.l
index 714c099d72f963d79af132aadf390e3af65f634d..cac74481a5a8c705dd7289593b343b11cd79e167 100644 (file)
--- a/gas/testsuite/gas/i386/arch-10-2.l
+++ b/gas/testsuite/gas/i386/arch-10-2.l
@@ -52,7 +52,7 @@ GAS LISTING .*
 [      ]*26[   ]+xgetbv
 [      ]*27[   ]+\# AES
 [      ]*28[   ]+aesenc  \(%ecx\),%xmm0
-[      ]*29[   ]+\# CLMUL
+[      ]*29[   ]+\# PCLMUL
 [      ]*30[   ]+pclmulqdq \$8,%xmm1,%xmm0
 [      ]*31[   ]+\# FMA
 [      ]*32[   ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7

diff --git a/gas/testsuite/gas/i386/arch-10-3.l b/gas/testsuite/gas/i386/arch-10-3.l
index 3315a98e57abf36dbc72dcdd91fc175480142e00..db521b3fcf025c738d1b26e47f0f9e695f7735c6 100644 (file)
--- a/gas/testsuite/gas/i386/arch-10-3.l
+++ b/gas/testsuite/gas/i386/arch-10-3.l
@@ -48,7 +48,7 @@ GAS LISTING .*
 [      ]*26[   ]+xgetbv
 [      ]*27[   ]+\# AES
 [      ]*28[   ]+aesenc  \(%ecx\),%xmm0
-[      ]*29[   ]+\# CLMUL
+[      ]*29[   ]+\# PCLMUL
 [      ]*30[   ]+pclmulqdq \$8,%xmm1,%xmm0
 [      ]*31[   ]+\# FMA
 [      ]*32[   ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7

diff --git a/gas/testsuite/gas/i386/arch-10-4.l b/gas/testsuite/gas/i386/arch-10-4.l
index eec46a3e59178a516cb03ed25db67ef0f9cd445f..f60e80b75de1d026e09b525eb8bc3b2e23b4b50b 100644 (file)
--- a/gas/testsuite/gas/i386/arch-10-4.l
+++ b/gas/testsuite/gas/i386/arch-10-4.l
@@ -46,7 +46,7 @@ GAS LISTING .*
 [      ]*26[   ]+xgetbv
 [      ]*27[   ]+\# AES
 [      ]*28[   ]+aesenc  \(%ecx\),%xmm0
-[      ]*29[   ]+\# CLMUL
+[      ]*29[   ]+\# PCLMUL
 [      ]*30[   ]+pclmulqdq \$8,%xmm1,%xmm0
 [      ]*31[   ]+\# FMA
 [      ]*32[   ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7

diff --git a/gas/testsuite/gas/i386/arch-10.d b/gas/testsuite/gas/i386/arch-10.d
index 60b44d45541daad67435145edbd61bc940de9e11..209949c108510e717e02f7c40963c52d878481a7 100644 (file)
--- a/gas/testsuite/gas/i386/arch-10.d
+++ b/gas/testsuite/gas/i386/arch-10.d
@@ -1,4 +1,4 @@
-#as: -march=i686+avx+vmx+smx+xsave+aes+clmul+fma+sse5+3dnowa+svme+padlock
+#as: -march=i686+avx+vmx+smx+xsave+aes+pclmul+fma+sse5+3dnowa+svme+padlock
 #objdump: -dw
 #name: i386 arch 10
 

diff --git a/gas/testsuite/gas/i386/arch-10.s b/gas/testsuite/gas/i386/arch-10.s
index afa3c3b44c86741b6c7a23dec590c4a04865301a..27f9f90dbf82e7b3f9938b39ebd72a69b20cf8da 100644 (file)
--- a/gas/testsuite/gas/i386/arch-10.s
+++ b/gas/testsuite/gas/i386/arch-10.s
@@ -26,7 +26,7 @@ getsec
 xgetbv
 # AES
 aesenc  (%ecx),%xmm0
-# CLMUL
+# PCLMUL
 pclmulqdq $8,%xmm1,%xmm0
 # FMA
 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7

diff --git a/gas/testsuite/gas/i386/clmul-intel.d b/gas/testsuite/gas/i386/clmul-intel.d
index cd29bb42d942acb659e5c489d54d3d919cdd925d..c311860066012b6981d7a4df052e82eb449b4285 100644 (file)
--- a/gas/testsuite/gas/i386/clmul-intel.d
+++ b/gas/testsuite/gas/i386/clmul-intel.d
@@ -1,6 +1,6 @@
 #source: clmul.s
 #objdump: -dw -Mintel
-#name: i386 CLMUL (Intel mode)
+#name: i386 PCLMUL (Intel mode)
 
 .*: +file format .*
 

diff --git a/gas/testsuite/gas/i386/clmul.d b/gas/testsuite/gas/i386/clmul.d
index be1a549e0843b95a89185f2395af32849b568386..b67e884a7ef0a5e8472e06a2d81cc869a9b01d75 100644 (file)
--- a/gas/testsuite/gas/i386/clmul.d
+++ b/gas/testsuite/gas/i386/clmul.d
@@ -1,5 +1,5 @@
 #objdump: -dw
-#name: i386 CLMUL
+#name: i386 PCLMUL
 
 .*: +file format .*
 

diff --git a/gas/testsuite/gas/i386/clmul.s b/gas/testsuite/gas/i386/clmul.s
index b77d5580710f5d65d98e7cc720e1078c53921529..2c5387963db776f35bc844a8e823169db9ffca0d 100644 (file)
--- a/gas/testsuite/gas/i386/clmul.s
+++ b/gas/testsuite/gas/i386/clmul.s
@@ -1,4 +1,4 @@
-# Check CLMUL new instructions.
+# Check PCLMUL new instructions.
 
        .text
 foo:

diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.d b/gas/testsuite/gas/i386/x86-64-arch-2.d
index 69cd92f49c7762c945060b51cfc28f32d88975b3..eac9dd3620ada91511a041e66ab01e9efb490d2e 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-arch-2.d
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.d
@@ -1,4 +1,4 @@
-#as: -march=generic64+avx+vmx+smx+xsave+aes+clmul+fma+sse5+3dnowa+svme+padlock
+#as: -march=generic64+avx+vmx+smx+xsave+aes+pclmul+fma+sse5+3dnowa+svme+padlock
 #objdump: -dw
 #name: x86-64 arch 2
 

diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.s b/gas/testsuite/gas/i386/x86-64-arch-2.s
index 73625e4c06521070f1f9a9c9afe5f53a5fa1f09c..11f5ebfb18e8861ec2fe26a740fedc99bab3024c 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-arch-2.s
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.s
@@ -26,7 +26,7 @@ getsec
 xgetbv
 # AES
 aesenc  (%rcx),%xmm0
-# CLMUL
+# PCLMUL
 pclmulqdq $8,%xmm1,%xmm0
 # FMA
 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7

diff --git a/gas/testsuite/gas/i386/x86-64-clmul-intel.d b/gas/testsuite/gas/i386/x86-64-clmul-intel.d
index 79a720c7bc91d7733f1df5678457ca74ae3e2c88..908904f34c5b9fc7e82b7fa352c02769de10df8f 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-clmul-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-clmul-intel.d
@@ -1,7 +1,7 @@
 #source: x86-64-clmul.s
 #as: -J
 #objdump: -dw -Mintel
-#name: x86-64 CLMUL (Intel mode)
+#name: x86-64 PCLMUL (Intel mode)
 
 .*: +file format .*
 

diff --git a/gas/testsuite/gas/i386/x86-64-clmul.d b/gas/testsuite/gas/i386/x86-64-clmul.d
index 5efd6065b99058b0436e5080480298f0c6be121d..83bb9cf34f0af4bdd9cb92faa1cdbe77d9d35215 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-clmul.d
+++ b/gas/testsuite/gas/i386/x86-64-clmul.d
@@ -1,6 +1,6 @@
 #as: -J
 #objdump: -dw
-#name: x86-64 CLMUL
+#name: x86-64 PCLMUL
 
 .*: +file format .*
 

diff --git a/gas/testsuite/gas/i386/x86-64-clmul.s b/gas/testsuite/gas/i386/x86-64-clmul.s
index a62107ccbcb4085abbf7c4e465d5eeaf00894900..0a61d982f022e8958a58da9962c46b7cd9e6bef6 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-clmul.s
+++ b/gas/testsuite/gas/i386/x86-64-clmul.s
@@ -1,4 +1,4 @@
-# Check 64bit CLMUL new instructions.
+# Check 64bit PCLMUL new instructions.
 
        .text
 foo:

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0c1be77b69ab9194bbda9291a9522aaa0fdbe2a4..9e89ebcafd6d095a3b630a9ca6300d9e520067b6 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,17 @@
+2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
+       with CPU_PCLMUL_FLAGS/CpuPCLMUL.
+       (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
+       * i386-opc.tbl: Likewise.
+
+       * i386-opc.h (CpuCLMUL): Renamed to ...
+       (CpuPCLMUL): This.
+       (CpuFMA): Updated.
+       (i386_cpu_flags): Replace cpuclmul with cpupclmul.
+
+       * i386-init.h: Regenerated.
+
 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386-dis.c (OP_E_register): New.

diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index b225e0653e791fe5d65c4bc822bcdf726c453235..12c8bb90ec3efb79dff9525dbacfee80e723292b 100644 (file)
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -104,8 +104,8 @@ static initializer cpu_flag_init [] =
     "CpuXsave" },
   { "CPU_AES_FLAGS",
     "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAES" },
-  { "CPU_CLMUL_FLAGS",
-    "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuCLMUL" },
+  { "CPU_PCLMUL_FLAGS",
+    "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuPCLMUL" },
   { "CPU_FMA_FLAGS",
     "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA" },
   { "CPU_3DNOW_FLAGS",
@@ -263,7 +263,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuABM),
   BITFIELD (CpuXsave),
   BITFIELD (CpuAES),
-  BITFIELD (CpuCLMUL),
+  BITFIELD (CpuPCLMUL),
   BITFIELD (CpuFMA),
   BITFIELD (CpuLM),
   BITFIELD (Cpu64),

diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h
index 11a88aa74b5f506edcd8e8651fc4fc05b415fba0..b6e7cfa482143503e87bee568a5c8cbe1941e68e 100644 (file)
--- a/opcodes/i386-init.h
+++ b/opcodes/i386-init.h
@@ -146,7 +146,7 @@
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1,  \
       0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
 
-#define CPU_CLMUL_FLAGS \
+#define CPU_PCLMUL_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1,  \
       0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
 

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 4ea2ec453b20f1f00c0a7fc4725e337222c82e7d..a3dd86377598514a0010406c05d8b15759f4f680 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -86,10 +86,10 @@
 #define CpuXsave       (CpuAVX + 1)
 /* AES support required */
 #define CpuAES         (CpuXsave + 1)
-/* CLMUL support required */
-#define CpuCLMUL       (CpuAES + 1)
+/* PCLMUL support required */
+#define CpuPCLMUL      (CpuAES + 1)
 /* FMA support required */
-#define CpuFMA         (CpuCLMUL + 1)
+#define CpuFMA         (CpuPCLMUL + 1)
 /* 64bit support available, used by -march= in assembler.  */
 #define CpuLM          (CpuFMA + 1)
 /* 64bit support required  */
@@ -142,7 +142,7 @@ typedef union i386_cpu_flags
       unsigned int cpuavx:1;
       unsigned int cpuxsave:1;
       unsigned int cpuaes:1;
-      unsigned int cpuclmul:1;
+      unsigned int cpupclmul:1;
       unsigned int cpufma:1;
       unsigned int cpulm:1;
       unsigned int cpu64:1;

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index dc71cf3a262f778761d893f09bad10fcc0b45ba0..411db32dab74eb3a0b3c034895f33cd2dc69a71b 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1722,13 +1722,13 @@ aesenclast, 2, 0x660f38dd, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_
 aesimc, 2, 0x660f38db, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 aeskeygenassist, 3, 0x660f3adf, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 
-// CLMUL
+// PCLMUL
 
-pclmulqdq, 3, 0x660f3a44, None, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-pclmullqlqdq, 2, 0x660f3a44, 0x0, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-pclmulhqlqdq, 2, 0x660f3a44, 0x1, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-pclmullqhqdq, 2, 0x660f3a44, 0x10, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
-pclmulhqhqdq, 2, 0x660f3a44, 0x11, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+pclmulqdq, 3, 0x660f3a44, None, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+pclmullqlqdq, 2, 0x660f3a44, 0x0, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+pclmulhqlqdq, 2, 0x660f3a44, 0x1, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+pclmullqhqdq, 2, 0x660f3a44, 0x10, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+pclmulhqhqdq, 2, 0x660f3a44, 0x11, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
 
 // AVX instructions.