(no commit message)

diff --git a/openpower/sv/rfc/ls002.mdwn b/openpower/sv/rfc/ls002.mdwn
index 4d1823d66753dd6be8bc3deaee9d70cc8fdb4040..7f96112bf266b526e13a37e2b07bd3a286080d2b 100644 (file)
--- a/openpower/sv/rfc/ls002.mdwn
+++ b/openpower/sv/rfc/ls002.mdwn
@@ -8,7 +8,7 @@
 
 **Target**: v3.2
 
-**Source: v3.0B**
+**Source**: v3.0B
 
 **Books and Section affected**:
 
@@ -48,3 +48,55 @@ Similar to `lxvkq` but extended to a full BF16 with one
 32-bit instruction and a full FP32 in two 32-bit instructions
 these instructions always save a Data Load and associated L1
 and TLB lookup.
+
+**Changes**
+
+Add the following instructions to Book I as a new Section 4.6.2.1
+
+Notes:
+
+1. There is no need for an Rc=1 variant because this is an immediate
+  loading instruction.
+2. There is no need for Special Registers (FP Flags) because this
+  is an immediate loading instruction.  No FPR Load Operations
+  alter `FPSCR` and neither does `lxvkq`
+
+----------------
+
+# Floating-Point Move Immediate
+
+`fmvis FRS, D`
+
+|  0-5   | 6-10 | 11-15 | 16-25 | 26-30 | 31  | Form    |
+|--------|------|-------|-------|-------|-----|---------|
+|  Major | FRS  | d1    | d0    | XO    | d2  | DX-Form |
+
+Pseudocode:
+
+    bf16 = d0 || d1 || d2 # create BF16 immediate
+    fp32 = bf16 || [0]*16 # convert BF16 to FP32
+    FRS = DOUBLE(fp32)    # convert FP32 to FP64
+
+Special registers altered:
+
+    None
+
+Reinterprets `D << 16` as a 32-bit float, which is then converted to a
+64-bit float and written to `FRS`.  This is equivalent to reinterpreting
+`D` as a `BF16` and converting to 64-bit float.
+
+Examples:
+
+```
+# clearing a FPR
+fmvis f4, 0 # writes +0.0 to f4
+# loading handy constants
+fmvis f4, 0x8000 # writes -0.0 to f4
+fmvis f4, 0x3F80 # writes +1.0 to f4
+fmvis f4, 0xBF80 # writes -1.0 to f4
+fmvis f4, 0xBFC0 # writes -1.5 to f4
+fmvis f4, 0x7FC0 # writes +qNaN to f4
+fmvis f4, 0x7F80 # writes +Infinity to f4
+fmvis f4, 0xFF80 # writes -Infinity to f4
+fmvis f4, 0x3FFF # writes +1.9921875 to f4
+```