Do not do sign extension in techmap; let packer do it

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 5444d842a9f5b73c6afe4d8149ac831b7acae0c4..70c2c42c6dca5de611cba4f5fcecd690ffb7a875 100644 (file)
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -196,24 +196,15 @@ module \$__mul (A, B, Y);
                        assign Y = partial_sum[n-1];\r
                end\r
                else begin \r
-                       if (A_SIGNED)\r
-                               wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);\r
-                       else\r
-                               wire [`DSP_A_MAXWIDTH-1:0] Aext = A;\r
-                       if (B_SIGNED)\r
-                               wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);\r
-                       else\r
-                               wire [`DSP_B_MAXWIDTH-1:0] Bext = B;\r
-\r
                        `DSP_NAME #(\r
                                .A_SIGNED(A_SIGNED),\r
                                .B_SIGNED(B_SIGNED),\r
-                               .A_WIDTH(`DSP_A_MAXWIDTH),\r
-                               .B_WIDTH(`DSP_B_MAXWIDTH),\r
-                               .Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),\r
+                               .A_WIDTH(A_WIDTH),\r
+                               .B_WIDTH(B_WIDTH),\r
+                               .Y_WIDTH(`MIN(Y_WIDTH,A_WIDTH+B_WIDTH)),\r
                        ) _TECHMAP_REPLACE_ (\r
-                               .A(Aext),\r
-                               .B(Bext),\r
+                               .A(A),\r
+                               .B(B),\r
                                .Y(Y)\r
                        );\r
                end\r