arm: Fix arm {,u}subvdi4 and usubvsi4 expanders [PR94286]

The following testcase ICEs, because these expanders will happily create
a SImode 0x80000000 CONST_INT, which is not valid RTL, as CONST_INTs need to
be sign extended from the mode precision to full HWI.

2020-03-24  Jakub Jelinek  <jakub@redhat.com>

	PR target/94286
	* config/arm/arm.md (subvdi4, usubvsi4, usubvdi4): Use gen_int_mode
	instead of GEN_INT.

	* gcc.dg/pr94286.c: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 976f87cd4086adfee91448f2d4a5ba146a4553e3..45b534b24ab41a06e3b0f24cfaaefbf5da6fd70c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,9 @@
 2020-03-24  Jakub Jelinek  <jakub@redhat.com>
 
+       PR target/94286
+       * config/arm/arm.md (subvdi4, usubvsi4, usubvdi4): Use gen_int_mode
+       instead of GEN_INT.
+
        PR debug/94285
        * tree-ssa-loop-manip.c (create_iv): If after, set stmt location to
        e->goto_locus even if gsi_bb (*incr_pos) contains only debug stmts.

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index b45109ed5292907dd2fb8ea075f994e510676c8f..1a7ea0d701e5677965574d877d0fe4b2f5bc149f 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1481,7 +1481,7 @@
     lo_op2 = force_reg (SImode, lo_op2);
   if (CONST_INT_P (lo_op2))
     emit_insn (gen_cmpsi2_addneg (lo_result, lo_op1, lo_op2,
-                                 GEN_INT (-INTVAL (lo_op2))));
+                                 gen_int_mode (-INTVAL (lo_op2), SImode)));
   else
     emit_insn (gen_subsi3_compare1 (lo_result, lo_op1, lo_op2));
 
@@ -1525,7 +1525,8 @@
     }
   else if (CONST_INT_P (operands[2]))
     emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2],
-                                 GEN_INT (-INTVAL (operands[2]))));
+                                 gen_int_mode (-INTVAL (operands[2]),
+                                               SImode)));
   else if (CONST_INT_P (operands[1]))
     {
       mode = CC_RSBmode;
@@ -1597,7 +1598,7 @@
     lo_op2 = force_reg (SImode, lo_op2);
   if (CONST_INT_P (lo_op2))
     emit_insn (gen_cmpsi2_addneg (lo_result, lo_op1, lo_op2,
-                                 GEN_INT (-INTVAL (lo_op2))));
+                                 gen_int_mode (-INTVAL (lo_op2), SImode)));
   else
     emit_insn (gen_subsi3_compare1 (lo_result, lo_op1, lo_op2));
 

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index de25dfb4f86802b048a1ead793fbf35bf6071be0..6747258de622a2f2986e0b63eac1717e60c1df64 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,8 @@
 2020-03-24  Jakub Jelinek  <jakub@redhat.com>
 
+       PR target/94286
+       * gcc.dg/pr94286.c: New test.
+
        PR debug/94285
        * gfortran.dg/pr94285.f90: New test.
 

diff --git a/gcc/testsuite/gcc.dg/pr94286.c b/gcc/testsuite/gcc.dg/pr94286.c
new file mode 100644 (file)
index 0000000..106cb75
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94286.c
@@ -0,0 +1,11 @@
+/* PR target/94286 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -g" } */
+
+unsigned a, b;
+
+int
+foo (void)
+{
+  return __builtin_sub_overflow (a, 0x80000000U, &b);
+}