(no commit message)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 8fe3f69d2a419f09849e7f1af7593cdd516d52a2..ceb5022cca27dc33b1a448780075b2365600f150 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -88,10 +88,11 @@ failure point, for
 exactly the same reasons for which it is mandatory in
 programming languages doing early-exit: to avoid
 damaging side-effects and to provide deterministic
-behsviour. Speculative testing of Condition
-Register Fields is permitted, as is speculative updating
+behaviour. Speculative testing of Condition
+Register Fields is permitted, as is speculative calculation
 of CTR, as long as, as usual in any Out-of-Order microarchitecture,
-that speculative testing is cancelled should an early-exit occur.*
+that speculative testing is cancelled should an early-exit occur.
+i.e. the speculation must be "precise": Program Order must be preserved*
 
 Also note that when early-exit occurs in Horizontal-first Mode,
 srcstep, dststep etc. are all reset, ready to begin looping from the
@@ -212,6 +213,11 @@ LRu and CTR-test modes are where SVP64 Branches subtly differ from
 Scalar v3.0B Branches. `bclr` for example will always update LR, whereas
 `sv.bclr/lru` will only update LR if the branch succeeds.
 
+*Programmer's Note: when using `bclr` with `LRu=1,LK=0` in Horizontal-First Mode,
+LR's value will be unconditionally overwritten after the first element,
+such that for execution (testing) of the second element, LR
+has the value `CIA+8`. This is covered in the `bclrl` example, below.
+
 Of special interest is that when using ALL Mode (Great Big AND
 of all Condition Tests), if `VL=0`,
 which is rare but can occur in Data-Dependent Modes, the Branch