re PR target/88070 (ICE in create_pre_exit, at mode-switching.c:438)

	PR target/88070
	* mode-switching.c (create_pre_exit): After reload, always split the
	fallthrough edge to the exit block.

testsuite/ChangeLog:

	PR target/88070
	* gcc.target/i386/pr88070.c: New test.

From-SVN: r266326

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 116e4b1f19dcda4201da0fa1f0480bf885cc6631..2ee021c62c330dbb373c38075e94b1757f7797fd 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-11-20  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/88070
+       * mode-switching.c (create_pre_exit): After reload, always split the
+       fallthrough edge to the exit block.
+
 2018-11-20  Jan Hubicka  <hubicka@ucw.cz>
 
        * ipa-devirt.c (add_type_duplicate): Do not ICE on incomplete enums.

diff --git a/gcc/mode-switching.c b/gcc/mode-switching.c
index 370a49e90a9c1c678e5cef35ce41a13944fe4cf6..589fbeb07425f2c9ef1eb1201cdff1277b4a49d8 100644 (file)
--- a/gcc/mode-switching.c
+++ b/gcc/mode-switching.c
@@ -248,8 +248,22 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
        gcc_assert (!pre_exit);
        /* If this function returns a value at the end, we have to
           insert the final mode switch before the return value copy
-          to its hard register.  */
-       if (EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) == 1
+          to its hard register.
+
+          x86 targets use mode-switching infrastructure to
+          conditionally insert vzeroupper instruction at the exit
+          from the function where there is no need to switch the
+          mode before the return value copy.  The vzeroupper insertion
+          pass runs after reload, so use !reload_completed as a stand-in
+          for x86 to skip the search for the return value copy insn.
+
+          N.b.: the code below assumes that the return copy insn
+          immediately precedes its corresponding use insn.  This
+          assumption does not hold after reload, since sched1 pass
+          can schedule the return copy insn away from its
+          corresponding use insn.  */
+       if (!reload_completed
+           && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) == 1
            && NONJUMP_INSN_P ((last_insn = BB_END (src_bb)))
            && GET_CODE (PATTERN (last_insn)) == USE
            && GET_CODE ((ret_reg = XEXP (PATTERN (last_insn), 0))) == REG)

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 94999db46954b47ef17ed13c114ccddca91ec773..1915d92af3b8c38fb15ff92d798cfb84ae60e4e2 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-11-20  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/88070
+       * gcc.target/i386/pr88070.c: New test.
+
 2018-11-20  Andreas Krebbel  <krebbel@linux.ibm.com>
 
        * gcc.target/s390/flogr-1.c: New test.

diff --git a/gcc/testsuite/gcc.target/i386/pr88070.c b/gcc/testsuite/gcc.target/i386/pr88070.c
new file mode 100644 (file)
index 0000000..5c545e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr88070.c
@@ -0,0 +1,12 @@
+/* PR target/88070 */
+/* { dg-do compile } */
+/* { dg-options "-O -fexpensive-optimizations -fnon-call-exceptions -fschedule-insns -fno-dce -fno-dse -mavx" } */
+
+typedef float vfloat2 __attribute__ ((__vector_size__ (2 * sizeof (float))));
+
+vfloat2
+test1float2 (float c)
+{
+  vfloat2 v = { c, c };
+  return v;
+}