assert(consts);
assert(max_comp <= 16);
- comp_mask = effective_writemask(alu, condense_writemask(alu->mask, bits));
+ comp_mask = effective_writemask(alu->op, condense_writemask(alu->mask, bits));
num_comp = util_bitcount(comp_mask);
fprintf(fp, "<");
uint32_t value = is_16 ? cons->u16[component] : cons->u32[component];
bool is_vector = false;
- unsigned mask = effective_writemask(&ins->alu, ins->mask);
+ unsigned mask = effective_writemask(ins->alu.op, ins->mask);
for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
/* We only care if this component is actually used */
/* Determines effective writemask, taking quirks and expansion into account */
static inline unsigned
-effective_writemask(midgard_vector_alu *alu, unsigned existing_mask)
+effective_writemask(midgard_alu_op op, unsigned existing_mask)
{
/* Channel count is off-by-one to fit in two-bits (0 channel makes no
* sense) */
- unsigned channel_count = GET_CHANNEL_COUNT(alu_opcode_props[alu->op].props);
+ unsigned channel_count = GET_CHANNEL_COUNT(alu_opcode_props[op].props);
/* If there is a fixed channel count, construct the appropriate mask */
src = vector_alu_from_unsigned(ins->alu.src2);
unsigned *swizzle = ins->swizzle[src_idx];
- unsigned comp_mask = effective_writemask(&ins->alu, ins->mask);
+ unsigned comp_mask = effective_writemask(ins->alu.op, ins->mask);
unsigned num_comp = util_bitcount(comp_mask);
unsigned max_comp = mir_components_for_type(ins->dest_type);
bool first = true;