aarch64.md (*aarch64_reg_<optab>_minus<mode>3): New pattern.

2017-10-07  Michael Collison <michael.collison@arm.com>

	* config/aarch64/aarch64.md (*aarch64_reg_<optab>_minus<mode>3):
	New pattern.

2017-10-07  Michael Collison <michael.collison@arm.com>

	* gcc.target/aarch64/var_shift_mask_2.c: New test.

From-SVN: r253520

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c12028bfca225d7ff01efe314d793aaa1d938d15..f1c391bc99ee6ab08ab5549fc1478a07312f5666 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2017-10-07  Michael Collison <michael.collison@arm.com>
+
+       * config/aarch64/aarch64.md (*aarch64_reg_<optab>_minus<mode>3):
+       New pattern.
+
 2017-10-07  Eric Botcazou  <ebotcazou@adacore.com>
 
        * builtins.def (BUILT_IN_SETJMP): Declare as library builtin instead

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index f8cdb063546afaf3ca977d078da6417729af88a6..389f2f9d31aadce4b3f758508279bdf2ffaf52e3 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4125,6 +4125,35 @@
   [(set_attr "type" "shift_reg")]
 )
 
+(define_insn_and_split "*aarch64_reg_<optab>_minus<mode>3"
+  [(set (match_operand:GPI 0 "register_operand" "=&r")
+       (ASHIFT:GPI
+         (match_operand:GPI 1 "register_operand" "r")
+         (minus:QI (match_operand 2 "const_int_operand" "n")
+                   (match_operand:QI 3 "register_operand" "r"))))]
+  "INTVAL (operands[2]) == GET_MODE_BITSIZE (<MODE>mode)"
+  "#"
+  "&& true"
+  [(const_int 0)]
+  {
+    rtx subreg_tmp = gen_lowpart (SImode, operands[3]);
+
+    rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
+              : gen_lowpart (SImode, operands[0]));
+
+    emit_insn (gen_negsi2 (tmp, subreg_tmp));
+
+    rtx and_op = gen_rtx_AND (SImode, tmp,
+                             GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1));
+
+    rtx subreg_tmp2 = gen_lowpart_SUBREG (QImode, and_op);
+
+    emit_insn (gen_<optab><mode>3 (operands[0], operands[1], subreg_tmp2));
+    DONE;
+  }
+  [(set_attr "length" "8")]
+)
+
 ;; Logical left shift using SISD or Integer instruction
 (define_insn "*aarch64_ashl_sisd_or_int_<mode>3"
   [(set (match_operand:GPI 0 "register_operand" "=r,r,w,w")

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 932a67f9855fb687275e527f73b91b50546d08b3..4c80e4bd9ecfd0e41a8eee91f28db55bb7cd1c31 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2017-10-07  Michael Collison <michael.collison@arm.com>
+
+       * gcc.target/aarch64/var_shift_mask_2.c: New test.
+
 2017-10-07  Paul Thomas  <pault@gcc.gnu.org>
 
        PR fortran/82375

diff --git a/gcc/testsuite/gcc.target/aarch64/var_shift_mask_2.c b/gcc/testsuite/gcc.target/aarch64/var_shift_mask_2.c
new file mode 100644 (file)
index 0000000..c1fe691
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/var_shift_mask_2.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+long long
+f1 (long long x, int i)
+{
+
+  return x >> (64 - i);
+}
+
+unsigned long long
+f2 (unsigned long long x, unsigned int i)
+{
+
+  return x >> (64 - i);
+}
+
+int
+f3 (int x, int i)
+{
+
+  return x >> (32 - i);
+}
+
+unsigned int
+f4 (unsigned int x, unsigned int i)
+{
+
+  return x >> (32 - i);
+}
+
+int
+f5 (int x, int i)
+{
+  return x << (32 - i);
+}
+
+long long
+f6 (long long x, int i)
+{
+  return x << (64 - i);
+}
+
+/* { dg-final { scan-assembler "lsl\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+/* { dg-final { scan-assembler "lsl\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+/* { dg-final { scan-assembler "lsr\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+/* { dg-final { scan-assembler "lsr\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+/* { dg-final { scan-assembler "asr\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+/* { dg-final { scan-assembler "asr\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+/* { dg-final { scan-assembler-times "neg\tw\[0-9\]+, w\[0-9\]+" 6 } } */
+/* { dg-final { scan-assembler-not "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */