Avoid generating wires for function args which are constant

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 00f8c8df67cd336814993436369df50110aea2de..101619c8cbf1c3685110e8492b61b5f63230d1be 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -483,6 +483,27 @@ static AstNode *make_packed_struct(AstNode *template_node, std::string &name)
        return wnode;
 }
 
+// check if a node or its children contains an assignment to the given variable
+static bool node_contains_assignment_to(const AstNode* node, const AstNode* var)
+{
+       if (node->type == AST_ASSIGN_EQ || node->type == AST_ASSIGN_LE) {
+               // current node is iteslf an assignment
+               log_assert(node->children.size() >= 2);
+               const AstNode* lhs = node->children[0];
+               if (lhs->type == AST_IDENTIFIER && lhs->str == var->str)
+                       return false;
+       }
+       for (const AstNode* child : node->children) {
+               // if this child shadows the given variable
+               if (child != var && child->str == var->str && child->type == AST_WIRE)
+                       break; // skip the remainder of this block/scope
+               // depth-first short circuit
+               if (!node_contains_assignment_to(child, var))
+                       return false;
+       }
+       return true;
+}
+
 // convert the AST into a simpler AST that has all parameters substituted by their
 // values, unrolled for-loops, expanded generate blocks, etc. when this function
 // is done with an AST it can be converted into RTLIL using genRTLIL().
@@ -3196,6 +3217,13 @@ skip_dynamic_range_lvalue_expansion:;
                                if ((child->is_input || child->is_output) && arg_count < children.size())
                                {
                                        AstNode *arg = children[arg_count++]->clone();
+                                       // convert purely constant arguments into localparams
+                                       if (child->is_input && child->type == AST_WIRE && arg->type == AST_CONSTANT && node_contains_assignment_to(decl, child)) {
+                                               wire->type = AST_LOCALPARAM;
+                                               wire->attributes.erase(ID::nosync);
+                                               wire->children.insert(wire->children.begin(), arg->clone());
+                                               continue;
+                                       }
                                        AstNode *wire_id = new AstNode(AST_IDENTIFIER);
                                        wire_id->str = wire->str;
                                        AstNode *assign = child->is_input ?

diff --git a/tests/various/const_arg_loop.v b/tests/various/const_arg_loop.v
new file mode 100644 (file)
index 0000000..8531856
--- /dev/null
+++ b/tests/various/const_arg_loop.v
@@ -0,0 +1,44 @@
+module top;
+       function automatic [31:0] operation1;
+               input [4:0] rounds;
+               input integer num;
+               integer i;
+               begin
+                       begin : shadow
+                               integer rounds;
+                               rounds = 0;
+                       end
+                       for (i = 0; i < rounds; i = i + 1)
+                               num = num * 2;
+                       operation1 = num;
+               end
+       endfunction
+
+       function automatic [31:0] operation2;
+               input [4:0] var;
+               input integer num;
+               begin
+                       var[0] = var[0] ^ 1;
+                       operation2 = num * var;
+               end
+       endfunction
+
+       wire [31:0] a;
+       assign a = 2;
+
+       parameter A = 3;
+
+       wire [31:0] x1;
+       assign x1 = operation1(A, a);
+
+       wire [31:0] x2;
+       assign x2 = operation2(A, a);
+
+// `define VERIFY
+`ifdef VERIFY
+    assert property (a == 2);
+    assert property (A == 3);
+    assert property (x1 == 16);
+    assert property (x2 == 4);
+`endif
+endmodule

diff --git a/tests/various/const_arg_loop.ys b/tests/various/const_arg_loop.ys
new file mode 100644 (file)
index 0000000..b039bda
--- /dev/null
+++ b/tests/various/const_arg_loop.ys
@@ -0,0 +1 @@
+read_verilog const_arg_loop.v