back.rtlil: sign of rhs and lhs of ${sshr,sshl,pow} don't need to match.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 298d2f9fc5eb17d1c9c569843e3bb7adc70281e8..7424c9d89836a0346fd896cf8bf8fb8efd10510d 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -485,7 +485,7 @@ class _RHSValueCompiler(_ValueCompiler):
         lhs, rhs = value.operands
         lhs_bits, lhs_sign = lhs.shape()
         rhs_bits, rhs_sign = rhs.shape()
-        if lhs_sign == rhs_sign:
+        if lhs_sign == rhs_sign or value.op in ("<<", ">>", "**"):
             lhs_wire = self(lhs)
             rhs_wire = self(rhs)
         else: