soc/uart: add configurable UART FIFO depth.

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index df1e1e1dcbf67ef3ea68a5400efface02c8f86a9..16f3902487645d5bf7c78ebfc944b11c4e9655e8 100644 (file)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -888,10 +888,10 @@ class LiteXSoC(SoC):
         self.csr.add(name + "_mem", use_loc_if_exists=True)
 
     # Add UART -------------------------------------------------------------------------------------
-    def add_uart(self, name, baudrate=115200):
+    def add_uart(self, name, baudrate=115200, fifo_depth=16):
         from litex.soc.cores import uart
         if name in ["stub", "stream"]:
-            self.submodules.uart = uart.UART()
+            self.submodules.uart = uart.UART(tx_fifo_depth=0, rx_fifo_depth=0)
             if name == "stub":
                 self.comb += self.uart.sink.ready.eq(1)
         elif name == "bridge":
@@ -914,7 +914,9 @@ class LiteXSoC(SoC):
                     pads     = self.platform.request(name),
                     clk_freq = self.sys_clk_freq,
                     baudrate = baudrate)
-            self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
+            self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
+                tx_fifo_depth = fifo_depth,
+                rx_fifo_depth = fifo_depth))
         self.csr.add("uart_phy", use_loc_if_exists=True)
         self.csr.add("uart", use_loc_if_exists=True)
         self.irq.add("uart", use_loc_if_exists=True)

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index e3f78e0d6e45d567954251edb44ffa0c3e866bda..776ceee0070927927e869a06f943debd729fed12 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -86,6 +86,7 @@ class SoCCore(LiteXSoC):
         with_uart                = True,
         uart_name                = "serial",
         uart_baudrate            = 115200,
+        uart_fifo_depth          = 16,
         # Timer parameters
         with_timer               = True,
         # Controller parameters
@@ -176,7 +177,7 @@ class SoCCore(LiteXSoC):
 
         # Add UART
         if with_uart:
-            self.add_uart(name=uart_name, baudrate=uart_baudrate)
+            self.add_uart(name=uart_name, baudrate=uart_baudrate, fifo_depth=uart_fifo_depth)
 
         # Add Timer
         if with_timer:
@@ -286,8 +287,8 @@ def soc_core_args(parser):
                         help="UART type/name (default=serial)")
     parser.add_argument("--uart-baudrate", default=None, type=int,
                         help="UART baudrate (default=115200)")
-    parser.add_argument("--uart-stub", default=False, type=bool,
-                        help="enable UART stub (default=False)")
+    parser.add_argument("--uart-fifo-depth", default=16, type=int,
+                        help="UART FIFO depth (default=16)")
     # Timer parameters
     parser.add_argument("--with-timer", default=None, type=bool,
                         help="with Timer (default=True)")

diff --git a/litex/tools/litex_gen.py b/litex/tools/litex_gen.py
index 39904ef642ad424967923a7a86bf88e7d4d221a4..b0bee6e27be6353acd27fcff706488e3d9f02ee7 100755 (executable)
--- a/litex/tools/litex_gen.py
+++ b/litex/tools/litex_gen.py
@@ -62,6 +62,7 @@ class LiteXCore(SoCMini):
         self.submodules.crg = CRG(platform.request("sys_clk"), rst=platform.request("sys_rst"))
 
         # SoCMini ----------------------------------------------------------------------------------
+        print(kwargs)
         SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # SPI Master
@@ -128,6 +129,7 @@ def soc_argdict(args):
         "bus",
         "with_pwm",
         "with_uart",
+        "uart_fifo_depth",
         "with_ctrl",
         "with_timer",
         "with_gpio",
@@ -151,6 +153,7 @@ def main():
     # Cores
     parser.add_argument("--with-pwm",              action="store_true",   help="Add PWM core")
     parser.add_argument("--with-uart",             action="store_true",   help="Add UART core")
+    parser.add_argument("--uart-fifo-depth",       default=16, type=int,  help="UART FIFO depth (default=16)")
     parser.add_argument("--with-ctrl",             action="store_true",   help="Add bus controller core")
     parser.add_argument("--with-timer",            action="store_true",   help="Add timer core")
     parser.add_argument("--with-spi-master",       action="store_true",   help="Add SPI master core")

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 8dd472c48c72520c50c34fc365f2319c1f7cb512..825a8367f9af73c373f8039bf74388f740b04636 100755 (executable)
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -176,7 +176,9 @@ class SimSoC(SoCSDRAM):
 
         # Serial -----------------------------------------------------------------------------------
         self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
-        self.submodules.uart = uart.UART(self.uart_phy)
+        self.submodules.uart = uart.UART(self.uart_phy,
+            tx_fifo_depth=kwargs["uart_fifo_depth"],
+            rx_fifo_depth=kwargs["uart_fifo_depth"])
         self.add_csr("uart")
         self.add_interrupt("uart")