R500_PVS_UCP_START : R300_PVS_UCP_START));
OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4);
for (i = 0; i < 6; i++) {
- OUT_CS_32F(clip->ucp[i][0]);
- OUT_CS_32F(clip->ucp[i][1]);
- OUT_CS_32F(clip->ucp[i][2]);
- OUT_CS_32F(clip->ucp[i][3]);
+ OUT_CS_TABLE(clip->ucp[i], 4);
}
OUT_CS_REG(R300_VAP_CLIP_CNTL, ((1 << clip->nr) - 1) |
R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
OUT_CS_REG(R300_US_CODE_OFFSET, code->code_offset);
OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4);
- for(i = 0; i < 4; ++i)
- OUT_CS(code->code_addr[i]);
+ OUT_CS_TABLE(code->code_addr, 4);
OUT_CS_REG_SEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
for (i = 0; i < code->alu.length; i++)
if (code->tex.length) {
OUT_CS_REG_SEQ(R300_US_TEX_INST_0, code->tex.length);
- for(i = 0; i < code->tex.length; ++i)
- OUT_CS(code->tex.inst[i]);
+ OUT_CS_TABLE(code->tex.inst, code->tex.length);
}
/* Emit immediates. */
R500_GA_US_VECTOR_INDEX_TYPE_CONST |
(i & R500_GA_US_VECTOR_INDEX_MASK));
OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
- OUT_CS_32F(data[0]);
- OUT_CS_32F(data[1]);
- OUT_CS_32F(data[2]);
- OUT_CS_32F(data[3]);
+ OUT_CS_TABLE(data, 4);
}
}
}
assert(constants->Constants[i].Type == RC_CONSTANT_EXTERNAL);
data = buf->constants[i];
- OUT_CS_32F(data[0]);
- OUT_CS_32F(data[1]);
- OUT_CS_32F(data[2]);
- OUT_CS_32F(data[3]);
+ OUT_CS_TABLE(data, 4);
}
END_CS;
}
R500_GA_US_VECTOR_INDEX_TYPE_CONST |
(i & R500_GA_US_VECTOR_INDEX_MASK));
OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
- OUT_CS_32F(data[0]);
- OUT_CS_32F(data[1]);
- OUT_CS_32F(data[2]);
- OUT_CS_32F(data[3]);
+ OUT_CS_TABLE(data, 4);
}
}
END_CS;
} else {
OUT_CS_REG_SEQ(R300_RS_IP_0, count);
}
+ OUT_CS_TABLE(rs->ip, count);
for (i = 0; i < count; i++) {
- OUT_CS(rs->ip[i]);
DBG(r300, DBG_DRAW, " : ip %d: 0x%08x\n", i, rs->ip[i]);
}
} else {
OUT_CS_REG_SEQ(R300_RS_INST_0, count);
}
+ OUT_CS_TABLE(rs->inst, count);
for (i = 0; i < count; i++) {
- OUT_CS(rs->inst[i]);
DBG(r300, DBG_DRAW, " : inst %d: 0x%08x\n", i, rs->inst[i]);
}
BEGIN_CS(size);
OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
+ OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
for (i = 0; i < streams->count; i++) {
- OUT_CS(streams->vap_prog_stream_cntl[i]);
DBG(r300, DBG_DRAW, " : prog_stream_cntl%d: 0x%08x\n", i,
streams->vap_prog_stream_cntl[i]);
}
OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
+ OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
for (i = 0; i < streams->count; i++) {
- OUT_CS(streams->vap_prog_stream_cntl_ext[i]);
DBG(r300, DBG_DRAW, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
streams->vap_prog_stream_cntl_ext[i]);
}
OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
- for (i = 0; i < code->length; i++) {
- OUT_CS(code->body.d[i]);
- }
+ OUT_CS_TABLE(code->body.d, code->length);
OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
for (i = imm_first; i < imm_end; i++) {
const float *data = vs->code.constants.Constants[i].u.Immediate;
- OUT_CS_32F(data[0]);
- OUT_CS_32F(data[1]);
- OUT_CS_32F(data[2]);
- OUT_CS_32F(data[3]);
+ OUT_CS_TABLE(data, 4);
}
}
END_CS;
OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
for (i = 0; i < count; i++) {
const float *data = buf->constants[i];
- OUT_CS_32F(data[0]);
- OUT_CS_32F(data[1]);
- OUT_CS_32F(data[2]);
- OUT_CS_32F(data[3]);
+ OUT_CS_TABLE(data, 4);
}
END_CS;
}