})
(define_insn "*movqi_internal"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m")
- (match_operand:QI 1 "general_operand" " 0,D*r, i,m,D"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m,*z,d")
+ (match_operand:QI 1 "general_operand" " 0,D*r, i,m,D,d,*z"))]
"(register_operand (operands[0], QImode)
|| register_operand (operands[1], QImode))"
{
return "";
case 1:
case 2:
+ case 5:
+ case 6:
return "mov %1,%0";
case 3:
case 4:
(const_int 13) (const_int 24))
(if_then_else (eq_attr "cpu" "am34")
(const_int 11) (const_int 22))
+ (const_int 11)
+ (const_int 11)
])]
)
})
(define_insn "*movhi_internal"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m")
- (match_operand:HI 1 "general_operand" " 0, i,D*r,m,D"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m,*z,d")
+ (match_operand:HI 1 "general_operand" " 0, i,D*r,m,D,d,*z"))]
"(register_operand (operands[0], HImode)
|| register_operand (operands[1], HImode))"
{
&& REGNO_EXTENDED_P (REGNO (operands[0]), 1))
return "movu %1,%0";
/* FALLTHRU */
+ case 5:
+ case 6:
case 2:
return "mov %1,%0";
case 3:
(const_int 13) (const_int 24))
(if_then_else (eq_attr "cpu" "am34")
(const_int 11) (const_int 22))
+ (if_then_else (eq_attr "cpu" "am34")
+ (const_int 11) (const_int 22))
+ (if_then_else (eq_attr "cpu" "am34")
+ (const_int 11) (const_int 22))
])]
)