add very basic PHY stimulator (to see HDD behaviour when we send primitives)

diff --git a/lib/sata/phy/k7sataphy/crg.py b/lib/sata/phy/k7sataphy/crg.py
index 2166fa7742718b8eb3ccef1e2c483f6fd9401bc2..40d607f2a284259d726affdaa3d85e064e66509e 100644 (file)
--- a/lib/sata/phy/k7sataphy/crg.py
+++ b/lib/sata/phy/k7sataphy/crg.py
@@ -80,9 +80,10 @@ class K7SATAPHYCRG(Module):
                # (SATA3) sata_rx recovered clk @ 300MHz from GTX RXOUTCLK
                # (SATA2) sata_rx recovered clk @ 150MHz from GTX RXOUTCLK
                # (SATA1) sata_rx recovered clk @ 150MHz from GTX RXOUTCLK
-               self.specials += [
-                       Instance("BUFG", i_I=gtx.rxoutclk, o_O=self.cd_sata_rx.clk),
-               ]
+               #self.specials += [
+               #       Instance("BUFG", i_I=gtx.rxoutclk, o_O=self.cd_sata_rx.clk),
+               #]
+               self.comb += self.cd_sata_tx.clk.eq(self.cd_sata_tx.clk)
                self.comb += [
                        gtx.rxusrclk.eq(self.cd_sata_rx.clk),
                        gtx.rxusrclk2.eq(self.cd_sata_rx.clk)

diff --git a/lib/sata/phy/k7sataphy/ctrl.py b/lib/sata/phy/k7sataphy/ctrl.py
index a3658c6e0059de578d69f7695f6c5e4885a5d867..11ccd3a82ce3d9b1ce5f8fe4b347ceb9db565952 100644 (file)
--- a/lib/sata/phy/k7sataphy/ctrl.py
+++ b/lib/sata/phy/k7sataphy/ctrl.py
@@ -117,6 +117,7 @@ class K7SATAPHYHostCtrl(Module):
                )
                fsm.act("SEND_ALIGN",
                        gtx.txelecidle.eq(0),
+                       gtx.rxalign.eq(1),
                        self.source.data.eq(primitives["ALIGN"]),
                        self.source.charisk.eq(0b0001),
                        If(non_align_cnt == 3,
@@ -125,8 +126,12 @@ class K7SATAPHYHostCtrl(Module):
                )
                fsm.act("READY",
                        gtx.txelecidle.eq(0),
+                       gtx.rxalign.eq(1),
                        self.source.data.eq(primitives["SYNC"]),
                        self.source.charisk.eq(0b0001),
+                       If(gtx.rxelecidle,
+                               NextState("RESET")
+                       ),
                        self.ready.eq(1),
                )
 

diff --git a/lib/sata/phy/k7sataphy/datapath.py b/lib/sata/phy/k7sataphy/datapath.py
index d28761f6c395684d1365d9fa1e6ae4ace81328cb..28ae7cf61cc1e864c8c4dba2ee1e04d82d0d341a 100644 (file)
--- a/lib/sata/phy/k7sataphy/datapath.py
+++ b/lib/sata/phy/k7sataphy/datapath.py
@@ -60,7 +60,7 @@ class K7SATAPHYDatapathRX(Module):
                # requirements:
                # due to the convertion ratio of 2, sys_clk need to be > sata_rx/2
                # source destination is always able to accept data (ack always 1)
-               fifo = AsyncFIFO(phy_description(32), 16)
+               fifo = AsyncFIFO(phy_description(32), 4)
                self.submodules.fifo = RenameClockDomains(fifo, {"write": "sata_rx", "read": "sys"})
                self.comb += [
                        fifo.sink.stb.eq(valid),
@@ -82,7 +82,7 @@ class K7SATAPHYDatapathTX(Module):
                # (SATA1) sys_clk to 75MHz sata_tx clk
                # requirements:
                # source destination is always able to accept data (ack always 1)
-               fifo = AsyncFIFO(phy_description(32), 16)
+               fifo = AsyncFIFO(phy_description(32), 4)
                self.submodules.fifo = RenameClockDomains(fifo, {"write": "sys", "read": "sata_tx"})
                self.comb += Record.connect(self.sink, fifo.sink)
 

diff --git a/targets/test.py b/targets/test.py
index 884c35d98b9adb6becbab1088dd3cb0fb0b63d9a..bc3e90543893cd9749e73ba9a21b174b3ab9e010 100644 (file)
--- a/targets/test.py
+++ b/targets/test.py
@@ -10,6 +10,7 @@ from miscope.uart2wishbone import UART2Wishbone
 from misoclib import identifier
 from lib.sata.common import *
 from lib.sata.phy.k7sataphy import K7SATAPHY
+from lib.sata.link.cont import SATACONTInserter, SATACONTRemover
 
 from migen.genlib.cdc import *
 
@@ -34,8 +35,8 @@ class _CRG(Module):
                                p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
                                i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
 
-                               # 166.66MHz
-                               p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
+                               # 100MHz
+                               p_CLKOUT0_DIVIDE=10, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
 
                                p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
 
@@ -106,7 +107,7 @@ class SimDesign(UART2WB):
        default_platform = "kc705"
 
        def __init__(self, platform, export_mila=False):
-               clk_freq = 166666*1000
+               clk_freq = 100*1000000
                UART2WB.__init__(self, platform, clk_freq)
                self.submodules.crg = _CRG(platform)
 
@@ -148,24 +149,44 @@ class ClockLeds(Module):
                                sata_tx_cnt.eq(sata_tx_cnt-1)
                        )
 
+class VeryBasicPHYStim(Module, AutoCSR):
+       def __init__(self, phy):
+               self._enable = CSRStorage()
+               self._tx_primitive = CSRStorage(32)
+               self._rx_primitive = CSRStatus(32)
+
+               self.submodules.cont_inserter = SATACONTInserter(phy_description(32))
+               self.submodules.cont_remover = SATACONTRemover(phy_description(32))
+               self.comb += [
+                       self.cont_inserter.source.connect(phy.sink),
+                       phy.source.connect(self.cont_remover.sink)
+               ]
+               self.sync += [
+                       self.cont_inserter.sink.stb.eq(1),
+                       self.cont_inserter.sink.charisk.eq(0b0001),
+                       If(self._enable.storage,
+                               self.cont_inserter.sink.data.eq(self._tx_primitive.storage),
+                               If(self.cont_remover.source.stb & (self.cont_remover.source.charisk == 0b0001),
+                                       self._rx_primitive.status.eq(self.cont_remover.source.data)
+                               )
+                       )
+               ]
+
 class TestDesign(UART2WB, AutoCSR):
        default_platform = "kc705"
        csr_map = {
                "mila":                         10,
+               "stim":             11
        }
        csr_map.update(UART2WB.csr_map)
 
        def __init__(self, platform, mila=True, export_mila=False):
-               clk_freq = 166666*1000
+               clk_freq = 100*1000000
                UART2WB.__init__(self, platform, clk_freq)
                self.submodules.crg = _CRG(platform)
 
-               self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, host=True, default_speed="SATA1")
-               self.comb += [
-                       self.sataphy_host.sink.stb.eq(1),
-                       self.sataphy_host.sink.data.eq(primitives["SYNC"]),
-                       self.sataphy_host.sink.charisk.eq(0b0001)
-               ]
+               self.submodules.sata_phy = K7SATAPHY(platform.request("sata_host"), clk_freq, host=True, default_speed="SATA1")
+               self.submodules.stim = VeryBasicPHYStim(self.sata_phy)
 
                self.submodules.clock_leds = ClockLeds(platform)
 
@@ -173,9 +194,9 @@ class TestDesign(UART2WB, AutoCSR):
                        import os
                        from miscope import MiLa, Term, UART2Wishbone
 
-                       gtx = self.sataphy_host.gtx
-                       ctrl = self.sataphy_host.ctrl
-                       crg = self.sataphy_host.crg
+                       gtx = self.sata_phy.gtx
+                       ctrl = self.sata_phy.ctrl
+                       crg = self.sata_phy.crg
 
                        debug = (
                                gtx.rxresetdone,
@@ -197,9 +218,13 @@ class TestDesign(UART2WB, AutoCSR):
                                ctrl.sink.charisk,
                                ctrl.align_detect,
 
-                               self.sataphy_host.source.stb,
-                               self.sataphy_host.source.data,
-                               self.sataphy_host.source.charisk,
+                               self.sata_phy.source.stb,
+                               self.sata_phy.source.data,
+                               self.sata_phy.source.charisk,
+
+                               self.sata_phy.sink.stb,
+                               self.sata_phy.sink.data,
+                               self.sata_phy.sink.charisk,
                        )
 
                        self.comb += platform.request("user_led", 2).eq(crg.ready)

diff --git a/test/test_stim.py b/test/test_stim.py
new file mode 100644 (file)
index 0000000..a379869
--- /dev/null
+++ b/test/test_stim.py
@@ -0,0 +1,42 @@
+from config import *
+import time
+
+primitives = {
+       "ALIGN" :       0x7B4A4ABC,
+       "CONT"  :       0X9999AA7C,
+       "SYNC"  :       0xB5B5957C,
+       "R_RDY" :       0x4A4A957C,
+       "R_OK"  :       0x3535B57C,
+       "R_ERR" :       0x5656B57C,
+       "R_IP"  :       0X5555B57C,
+       "X_RDY" :       0x5757B57C,
+       "CONT"  :       0x9999AA7C,
+       "WTRM"  :       0x5858B57C,
+       "SOF"   :       0x3737B57C,
+       "EOF"   :       0xD5D5B57C,
+       "HOLD"  :       0xD5D5AA7C,
+       "HOLDA" :       0X9595AA7C
+}
+
+def decode_primitive(dword):
+       for k, v in primitives.items():
+               if dword == v:
+                       return k
+       return ""
+
+wb.open()
+regs = wb.regs
+###
+regs.stim_enable.write(1)
+regs.stim_tx_primitive.write(primitives["SYNC"])
+for i in range(16):
+       rx = regs.stim_rx_primitive.read()
+       print("rx: %08x %s" %(rx, decode_primitive(rx)))
+       time.sleep(0.1)
+regs.stim_tx_primitive.write(primitives["R_RDY"])
+for i in range(16):
+       rx = regs.stim_rx_primitive.read()
+       print("rx: %08x %s" %(rx, decode_primitive(rx)))
+       time.sleep(0.1)
+###
+wb.close()