pan/mdg: Implement raw colourbuf loads on T720
authorAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Sat, 30 May 2020 01:11:11 +0000 (21:11 -0400)
committerMarge Bot <eric+marge@anholt.net>
Mon, 1 Jun 2020 15:46:23 +0000 (15:46 +0000)
Uses a similar path to the fp16 cbuf loads on T760. It should make sense
given the symmetry with T860.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5265>

src/panfrost/midgard/midgard.h
src/panfrost/midgard/midgard_compile.c
src/panfrost/midgard/midgard_ops.c

index 1dfa7e9f257a79b6173d83b943a5b7b4acc562ff..63f2fa2f5860f689af238d56aac7a674148c60c5 100644 (file)
@@ -479,6 +479,7 @@ typedef enum {
 
         /* Old version of midgard_op_ld_color_buffer_as_fp16, for T720 */
         midgard_op_ld_color_buffer_as_fp16_old = 0x9D,
+        midgard_op_ld_color_buffer_32u_old = 0x9E,
 
         /* The distinction between these ops is the alignment requirement /
          * accompanying shift. Thus, the offset to ld_ubo_int4 is in 16-byte
index 233f23f44d7893f5df27d3ecc75deef67f292423..e1d6cac7672f55593addc471f6b1b4e3a9abdd95 100644 (file)
@@ -1581,15 +1581,19 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
                                 midgard_op_ld_color_buffer_as_fp16_old :
                                 midgard_op_ld_color_buffer_as_fp16;
 
-                        if (old_blend) {
-                                ld.load_store.address = 1;
-                                ld.load_store.arg_2 = 0x1E;
-                        }
-
                         for (unsigned c = 4; c < 16; ++c)
                                 ld.swizzle[0][c] = 0;
 
                         ld.dest_type = nir_type_float16;
+
+                        if (old_blend) {
+                                ld.load_store.address = 1;
+                                ld.load_store.arg_2 = 0x1E;
+                        }
+                } else if (old_blend) {
+                        ld.load_store.op = midgard_op_ld_color_buffer_32u_old;
+                        ld.load_store.address = 16;
+                        ld.load_store.arg_2 = 0x1E;
                 }
 
                 emit_mir_instruction(ctx, ld);
index dc30eceec2dfccd87af1e454de43f8c01b8b1283..3055f0b93f537ccd59cd8cb7ddbe2a2f0580dd88 100644 (file)
@@ -227,6 +227,7 @@ struct mir_ldst_op_props load_store_opcode_props[256] = {
         [midgard_op_ld_vary_32u] = {"ld_vary_32u", M32},
 
         [midgard_op_ld_color_buffer_32u]  = {"ld_color_buffer_32u",  M32},
+        [midgard_op_ld_color_buffer_32u_old]  = {"ld_color_buffer_32u_old",  M32},
         [midgard_op_ld_color_buffer_as_fp16] = {"ld_color_buffer_as_fp16", M16},
         [midgard_op_ld_color_buffer_as_fp16_old] = {"ld_color_buffer_as_fp16_old", M16 | LDST_SPECIAL_MASK},