boards/targets: add keep attribute directly in crg

This makes it systematic and avoid having to add it later.

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 115df401780ed8f849d3f5a2356e1372908fcca5..c5a20ea2d3a2ed55c9afe55e0750a66e59ab39da 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -26,6 +26,13 @@ class _CRG(Module):
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200 = ClockDomain()
 
+        # # #
+
+        self.cd_sys.clk.attr.add("keep")
+        self.cd_sys4x.clk.attr.add("keep")
+        self.cd_sys4x_dqs.clk.attr.add("keep")
+        self.cd_clk200.clk.attr.add("keep")
+
         self.submodules.pll = pll = S7PLL(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk100"), 100e6)
@@ -95,10 +102,8 @@ class EthernetSoC(BaseSoC):
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 
-        self.crg.cd_sys.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
-        self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 80.0)
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 80.0)
         self.platform.add_false_path_constraints(

diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py
index 70b4a5c96e89c6449ac8a6c30f3047d9b91cf0c0..c51c1a1164b3623d85bcae521d3acbb481979ea9 100755 (executable)
--- a/litex/boards/targets/de0nano.py
+++ b/litex/boards/targets/de0nano.py
@@ -60,6 +60,12 @@ class _CRG(Module):
         self.clock_domains.cd_sys_ps = ClockDomain()
         self.clock_domains.cd_por = ClockDomain(reset_less=True)
 
+        # # #
+
+        self.cd_sys.clk.attr.add("keep")
+        self.cd_sys_ps.clk.attr.add("keep")
+        self.cd_por.clk.attr.add("keep")
+
         clk50 = platform.request("clk50")
 
         sys_pll = _ALTPLL(20, "sys", 0, "NORMAL")

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index afe3992bbfdaa8dbb208ff8800eb66dfd878f84a..150f830b538cb7d0bf1250d64048f3ecd9108f74 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -25,6 +25,12 @@ class _CRG(Module):
         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200 = ClockDomain()
 
+        # # #
+
+        self.cd_sys.clk.attr.add("keep")
+        self.cd_sys4x.clk.attr.add("keep")
+        self.cd_clk200.clk.attr.add("keep")
+
         self.submodules.pll = pll = S7MMCM(speedgrade=-2)
         self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
         pll.register_clkin(platform.request("clk200"), 200e6)
@@ -87,10 +93,8 @@ class EthernetSoC(BaseSoC):
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 
-        self.crg.cd_sys.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
-        self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
         self.platform.add_false_path_constraints(

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index dc5d4e22c5744385625d6d9a3ccc79411fbb5e35..0493db8c6112cb99cbcb6a5d4a9eb6a0bb02e5db 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -25,6 +25,12 @@ class _CRG(Module):
         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200 = ClockDomain()
 
+        # # #
+
+        self.cd_sys.clk.attr.add("keep")
+        self.cd_sys4x.clk.attr.add("keep")
+        self.cd_clk200.clk.attr.add("keep")
+
         self.submodules.pll = pll = S7MMCM(speedgrade=-2)
         self.comb += pll.reset.eq(platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk200"), 200e6)
@@ -87,10 +93,8 @@ class EthernetSoC(BaseSoC):
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 
-        self.crg.cd_sys.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
-        self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
         self.platform.add_false_path_constraints(

diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index 502af29ee5ef67645c6785333ba83a96d8eb8543..d676cff3d45e0f4215d1944a537c5193f105509b 100755 (executable)
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -26,6 +26,13 @@ class _CRG(Module):
         self.clock_domains.cd_clk200 = ClockDomain()
         self.clock_domains.cd_ic = ClockDomain()
 
+        # # #
+
+        self.cd_sys.clk.attr.add("keep")
+        self.cd_sys4x.clk.attr.add("keep")
+        self.cd_clk200.clk.attr.add("keep")
+        self.cd_ic.clk.attr.add("keep")
+
         self.submodules.pll = pll = USMMCM(speedgrade=-2)
         self.comb += pll.reset.eq(platform.request("cpu_reset"))
         self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
@@ -126,7 +133,6 @@ class EthernetSoC(BaseSoC):
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 
-        self.crg.cd_sys.clk.attr.add("keep")
         self.ethphy.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.cd_eth_tx.clk.attr.add("keep")
         self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6)

diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py
index 00cc506cf544af92c5448c7440d625fa953305e4..2f3ed445da4979a7bfad92348f276a57e6aab0df 100755 (executable)
--- a/litex/boards/targets/minispartan6.py
+++ b/litex/boards/targets/minispartan6.py
@@ -21,6 +21,11 @@ class _CRG(Module):
         self.clock_domains.cd_sys = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain()
 
+        # # #
+
+        self.cd_sys.clk.attr.add("keep")
+        self.cd_sys_ps.clk.attr.add("keep")
+
         f0 = 32*1000000
         clk32 = platform.request("clk32")
         clk32a = Signal()

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index e120982807e149d0e93e69fb2e89bb55793d0cc4..661aba1826228b223d25f920b0fa660897751fcc 100755 (executable)
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -25,6 +25,14 @@ class _CRG(Module):
         self.clock_domains.cd_clk200 = ClockDomain()
         self.clock_domains.cd_clk100 = ClockDomain()
 
+        # # #
+
+        self.cd_sys.clk.attr.add("keep")
+        self.cd_sys2x.clk.attr.add("keep")
+        self.cd_sys2x_dqs.clk.attr.add("keep")
+        self.cd_clk200.clk.attr.add("keep")
+        self.cd_clk100.clk.attr.add("keep")
+
         self.submodules.pll = pll = S7MMCM(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk100"), 100e6)

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 902d2ec50492a524d90b72b78f202fcef0987c6b..db94b9f6343711497366a6f41c80e1e61d5b9676 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -27,6 +27,14 @@ class _CRG(Module):
         self.clock_domains.cd_clk200 = ClockDomain()
         self.clock_domains.cd_clk100 = ClockDomain()
 
+        # # #
+
+        self.cd_sys.clk.attr.add("keep")
+        self.cd_sys4x.clk.attr.add("keep")
+        self.cd_sys4x_dqs.clk.attr.add("keep")
+        self.cd_clk200.clk.attr.add("keep")
+        self.cd_clk100.clk.attr.add("keep")
+
         self.submodules.pll = pll = S7MMCM(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk100"), 100e6)
@@ -91,10 +99,8 @@ class EthernetSoC(BaseSoC):
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 
-        self.crg.cd_sys.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
-        self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
         self.platform.add_false_path_constraints(

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index ed7e7350cb38a7574dd9241342288526d38b3c9e..ec54c406e3bceda26c4141a31a87ec0275978441 100755 (executable)
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -23,6 +23,9 @@ class _CRG(Module):
 
         # # #
 
+        self.cd_sys.clk.attr.add("keep")
+        self.cd_sys_ps.clk.attr.add("keep")
+
         # clk / rst
         clk25 = platform.request("clk25")
         rst = platform.request("rst")

diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index f82e42e809636a9162a009cee03cf1231faaa304..6331d4a1289b45272f860919ec3c00299753375c 100755 (executable)
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -30,6 +30,12 @@ class _CRG(Module):
 
         # # #
 
+        self.cd_init.clk.attr.add("keep")
+        self.cd_por.clk.attr.add("keep")
+        self.cd_sys.clk.attr.add("keep")
+        self.cd_sys2x.clk.attr.add("keep")
+        self.cd_sys2x_i.clk.attr.add("keep")
+
         self.stop = Signal()
 
         # clk / rst