Merge branch 'eddie/xaig_dff_adff' into xaig_dff

diff --cc techlibs/xilinx/abc9_map.v
Simple merge

diff --cc tests/simple_abc9/abc9.v
index 13c505eececc7cc9a3d194c678d64633f04ac25f,58596d701b2a59c691be31710ecb5bebf1c32357..596a525017284ad208f9352a1fb8a6ba29e5ec74
--- 1/tests/simple_abc9/abc9.v
--- 2/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@@ -268,12 -268,14 +268,23 @@@ assign o = { 1'b1, 1'bx }
  assign p = { 1'b1, 1'bx, 1'b0 };
  endmodule
  
- module abc9_test029(input clk1, clk2, d, output reg q1, q2);
+ module abc9_test029(input clk, d, r, output reg q);
+ always @(posedge clk or posedge r)
+     if (r) q <= 1'b0;
+     else q <= d;
+ endmodule
+ 
+ module abc9_test030(input clk, d, r, output reg q);
+ always @(negedge clk or posedge r)
+     if (r) q <= 1'b1;
+     else q <= d;
+ endmodule
++
++module abc9_test032(input clk1, clk2, d, output reg q1, q2);
 +always @(posedge clk1) q1 <= d;
 +always @(negedge clk2) q2 <= q1;
 +endmodule
 +
- module abc9_test030(input clk, d, output reg q1, q2);
++module abc9_test033(input clk, d, output reg q1, q2);
 +always @(posedge clk) q1 <= d;
 +always @(posedge clk) q2 <= q1;
- endmodule