fix(ls003.mdwn): Using desc from PowerISA as template for divmod2du

diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn
index 7fb86463b28a397ae79b6c0fcdc3615e60b12ec9..77416fd1ed70d43e9a67921c14fbb1f7a38f6287 100644 (file)
--- a/openpower/sv/rfc/ls003.mdwn
+++ b/openpower/sv/rfc/ls003.mdwn
@@ -191,6 +191,21 @@ Special registers altered:
 
     None
 
+The 128-bit dividend is (RA) || (RC). The 64-bit divisor is
+(RB). If the quotient can be represented in 64 bits, it is
+placed into register RT. The modulo is placed into register RS.
+RS is implictly defined as the same register as RC, similarly to maddedu.
+
+The instruction is only defined where both conditions are true:
+
+* (RA) < (RB) (unsigned comparison)
+* (RB) is NOT 0 (not divide-by-0)
+
+If these conditions are not met, RT is set to all 1's, RS to all 0's.
+
+Both operands, quotient, and modulo are interpreted as unsigned integers.
+
+
 Divide/Modulo Quad-Double Unsigned is another VA-Form instruction
 that is near-identical to `divdeu` except that: