i386: Use ix86_output_ssemov for SImode TYPE_SSEMOV

There is no need to set mode attribute to XImode since ix86_output_ssemov
can properly encode xmm16-xmm31 registers with and without AVX512VL.

Remove ext_sse_reg_operand since it is no longer needed.

gcc/

	PR target/89229
	* config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov
	for TYPE_SSEMOV.  Remove ext_sse_reg_operand and TARGET_AVX512VL
	check.
	* config/i386/predicates.md (ext_sse_reg_operand): Removed.

gcc/testsuite/

	PR target/89229
	* gcc.target/i386/pr89229-7a.c: New test.
	* gcc.target/i386/pr89229-7b.c: Likewise.
	* gcc.target/i386/pr89229-7c.c: Likewise.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 81582dd4f8c13b885ba8298c003de6192fb94bf9..8ae1371c7185dece64f54641c905301b48a9a423 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2020-03-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/89229
+       * config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov
+       for TYPE_SSEMOV.  Remove ext_sse_reg_operand and TARGET_AVX512VL
+       check.
+       * config/i386/predicates.md (ext_sse_reg_operand): Removed.
+
 2020-03-16  Jakub Jelinek  <jakub@redhat.com>
 
        PR debug/94167

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index af39f90c68e3d379fe51dc44fd0838a72aea8864..3051624d89fdaa01c4a95d7546a99df70723f350 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -2261,25 +2261,7 @@
       gcc_unreachable ();
 
     case TYPE_SSEMOV:
-      switch (get_attr_mode (insn))
-       {
-       case MODE_SI:
-          return "%vmovd\t{%1, %0|%0, %1}";
-       case MODE_TI:
-         return "%vmovdqa\t{%1, %0|%0, %1}";
-       case MODE_XI:
-         return "vmovdqa32\t{%g1, %g0|%g0, %g1}";
-
-       case MODE_V4SF:
-         return "%vmovaps\t{%1, %0|%0, %1}";
-
-       case MODE_SF:
-         gcc_assert (!TARGET_AVX);
-          return "movss\t{%1, %0|%0, %1}";
-
-       default:
-         gcc_unreachable ();
-       }
+      return ix86_output_ssemov (insn, operands);
 
     case TYPE_MMX:
       return "pxor\t%0, %0";
@@ -2345,10 +2327,7 @@
      (cond [(eq_attr "alternative" "2,3")
              (const_string "DI")
            (eq_attr "alternative" "8,9")
-             (cond [(ior (match_operand 0 "ext_sse_reg_operand")
-                         (match_operand 1 "ext_sse_reg_operand"))
-                      (const_string "XI")
-                    (match_test "TARGET_AVX")
+             (cond [(match_test "TARGET_AVX")
                       (const_string "TI")
                     (ior (not (match_test "TARGET_SSE2"))
                          (match_test "optimize_function_for_size_p (cfun)"))

diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 1119366d54eaaf5d374ffe40029837fc8eb5c943..71f4cb1193cdca6ed5a5a32a03e9dd024fbff68f 100644 (file)
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -61,11 +61,6 @@
   (and (match_code "reg")
        (match_test "SSE_REGNO_P (REGNO (op))")))
 
-;; True if the operand is an AVX-512 new register.
-(define_predicate "ext_sse_reg_operand"
-  (and (match_code "reg")
-       (match_test "EXT_REX_SSE_REGNO_P (REGNO (op))")))
-
 ;; Return true if op is a QImode register.
 (define_predicate "any_QIreg_operand"
   (and (match_code "reg")

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 0f87a04d10017fdf740207a0ed79a30f66b5d460..b133809a188d2a4a28783ca8ea8b9cfddcdd2f89 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2020-03-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/89229
+       * gcc.target/i386/pr89229-7a.c: New test.
+       * gcc.target/i386/pr89229-7b.c: Likewise.
+       * gcc.target/i386/pr89229-7c.c: Likewise.
+
 2020-03-16  Iain Buclaw  <ibuclaw@gdcproject.org>
 
        * gdc.dg/asm1.d: Add new test for ICE in asm parser.

diff --git a/gcc/testsuite/gcc.target/i386/pr89229-7a.c b/gcc/testsuite/gcc.target/i386/pr89229-7a.c
new file mode 100644 (file)
index 0000000..fd56f44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89229-7a.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake-avx512" } */
+
+extern int i;
+
+int
+foo1 (void)
+{
+  register int xmm16 __asm ("xmm16") = i;
+  asm volatile ("" : "+v" (xmm16));
+  register int xmm17 __asm ("xmm17") = xmm16;
+  asm volatile ("" : "+v" (xmm17));
+  return xmm17;
+}
+
+/* { dg-final { scan-assembler-times "vmovdqa32\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" 1 } } */
+/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */

diff --git a/gcc/testsuite/gcc.target/i386/pr89229-7b.c b/gcc/testsuite/gcc.target/i386/pr89229-7b.c
new file mode 100644 (file)
index 0000000..d3a56e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89229-7b.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake-avx512 -mno-avx512vl" } */
+
+#include "pr89229-7a.c"
+
+/* { dg-final { scan-assembler-times "vmovdqa32\[^\n\r]*zmm1\[67]\[^\n\r]*zmm1\[67]" 1 } } */

diff --git a/gcc/testsuite/gcc.target/i386/pr89229-7c.c b/gcc/testsuite/gcc.target/i386/pr89229-7c.c
new file mode 100644 (file)
index 0000000..e14634e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89229-7c.c
@@ -0,0 +1,7 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake-avx512 -mprefer-vector-width=512" } */
+
+#include "pr89229-7a.c"
+
+/* { dg-final { scan-assembler-times "vmovdqa32\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" 1 } } */
+/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */